Xeon Phi was the last remnant of the first GPU architecture I worked on. It was evolved from Larrabee, meant to run DX11 graphics workloads. The first Phi was effectively the Larrabee chip but with the texture sampling hardware fused off. The remnants of that work are now living on in the AVX512 instruction set. The principal problem with Larrabee was that the ring bus connecting some 60+ ring stops was *so wide* (512 bits bidirectional = 1024 bits!) that it consumed too much power. It was more flexible than it needed to be compared to a GPU memory controller/crossbar, and its power consumption couldn't be reduced sufficiently to make it a useful architecture for the mobile market. Instead, graphics continued on the older Intel embedded graphics path. Frankly, I'm amazed that Intel followed through with 2 more revisions of Xeon Phi before canning it. In all honestly, the core choice for the CPU (P54C) was nice for micro-optimized predictability of instruction execution times and reasoning about hazards, but Intel's architectural mastery of micro-op recompilation and out-of-order pipelines really trumps what the compilers were doing once it was removed from the graphics space.
On Fri, Dec 27, 2024 at 1:12 PM Kurt H Maier via 9fans <9fans@9fans.net> wrote: > I always thought NIX would have been a good fit for Xeon Phi MICs, since > part of the bringup involved shipping an entire linux system to the card > for booting anyway. Sadly, Intel (as usual) gave up on the architecture > about ten minutes after release. > ------------------------------------------ 9fans: 9fans Permalink: https://9fans.topicbox.com/groups/9fans/T7692a612f26c8ec5-Md2d5c0b29b8a6dfa47a3798f Delivery options: https://9fans.topicbox.com/groups/9fans/subscription
