On 23.07.2019 18:45, Andrew Cooper wrote: > On 23/07/2019 17:09, Jan Beulich wrote: >> On 23.07.2019 17:48, Roger Pau Monne wrote: >>> Current code only prevents mapping the io-apic page into the guest >>> physical memory map. Expand the range to be 0xFECx_xxxx as described >>> in the Intel 3 Series Chipset Datasheet section 3.3.1 "APIC >>> Configuration Space (FEC0_0000h–FECF_FFFFh)". >>> >>> AMD also lists this address range in the AMD SR5690 Databook, section >>> 2.4.2 "Non-SB IOAPIC Support". >> But that's chipset specific. I don't think we can blindly assume >> this range. > > The IO-APIC has always lived in that region since its introduction, and > the location isn't even configurable on newer chipsets (If I've read the > SAD routing rules in Skylake correctly. All that can be configured is > multiple IO-APICs being mapped adjacent to each other.)
I'm pretty sure I've seen IO-APICs outside that range. I'm not entirely opposed to a change like this, but I think it wants to come with better description (taking into account the chipset- rather than architecture-defined-ness) and either retaining of the loop the patch currently replaces, or an explanation why the loop is strictly unnecessary. Jan _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel
