On 23/07/2019 17:09, Jan Beulich wrote: > On 23.07.2019 17:48, Roger Pau Monne wrote: >> Current code only prevents mapping the io-apic page into the guest >> physical memory map. Expand the range to be 0xFECx_xxxx as described >> in the Intel 3 Series Chipset Datasheet section 3.3.1 "APIC >> Configuration Space (FEC0_0000h–FECF_FFFFh)". >> >> AMD also lists this address range in the AMD SR5690 Databook, section >> 2.4.2 "Non-SB IOAPIC Support". > But that's chipset specific. I don't think we can blindly assume > this range.
The IO-APIC has always lived in that region since its introduction, and the location isn't even configurable on newer chipsets (If I've read the SAD routing rules in Skylake correctly. All that can be configured is multiple IO-APICs being mapped adjacent to each other.) While this isn't the inbound MSI range (and definitely fixed in the architecture), it isn't plausibly going to change. ~Andrew _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel
