>>> On 20.12.18 at 14:14, <pu...@hygon.cn> wrote: > The Hygon Dhyana CPU supports lots of MSRs(such as perf event select and > counter MSRs, hardware configuration MSR, MMIO configuration base address > MSR, MPERF/APERF MSRs) as AMD CPU does, so add Hygon Dhyana support to the > PV emulation infrastructure by using the code path of AMD. > > As hygon.c needs to write the load-store configuration(LS_CFG) MSR, so add > new case in write_msr to handle this situation.
Which hygon.c do you mean here? This addition, if valid at all, clearly needs its own patch and justification, the more that you permit access (even if only for Dom0) on AMD as well. Jan _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel
