The Hygon Dhyana processor has the methold to get the last exception
source IP from MSR0000_01DD. So add support for it if the boot param
ler is true.
Signed-off-by: Pu Wen <pu...@hygon.cn>
---
xen/arch/x86/traps.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 05ddc39..bd5c16e 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -1973,6 +1973,8 @@ static unsigned int calc_ler_msr(void)
return MSR_IA32_LASTINTFROMIP;
}
break;
+ case X86_VENDOR_HYGON:
+ return MSR_IA32_LASTINTFROMIP;
}
return 0;
--
2.7.4
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