On 14/08/2025 2:19 pm, Jan Beulich wrote:
> On 14.08.2025 13:20, Jan Beulich wrote:
>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>> --- a/xen/include/public/arch-x86/cpufeatureset.h
>>> +++ b/xen/include/public/arch-x86/cpufeatureset.h
>>> @@ -310,7 +310,10 @@ XEN_CPUFEATURE(ARCH_PERF_MON, 10*32+8) /*   
>>> Architectural Perfmon */
>>>  XEN_CPUFEATURE(FZRM,         10*32+10) /*A  Fast Zero-length REP MOVSB */
>>>  XEN_CPUFEATURE(FSRS,         10*32+11) /*A  Fast Short REP STOSB */
>>>  XEN_CPUFEATURE(FSRCS,        10*32+12) /*A  Fast Short REP CMPSB/SCASB */
>>> +XEN_CPUFEATURE(FRED,         10*32+17) /*   Fast Return and Event Delivery 
>>> */
>>> +XEN_CPUFEATURE(LKGS,         10*32+18) /*   Load Kernel GS instruction */
>>>  XEN_CPUFEATURE(WRMSRNS,      10*32+19) /*S  WRMSR Non-Serialising */
>>> +XEN_CPUFEATURE(NMI_SRC,      10*32+20) /*   NMI-Source Reporting */
>>>  XEN_CPUFEATURE(AMX_FP16,     10*32+21) /*   AMX FP16 instruction */
>>>  XEN_CPUFEATURE(AVX_IFMA,     10*32+23) /*A  AVX-IFMA Instructions */
>>>  XEN_CPUFEATURE(LAM,          10*32+26) /*   Linear Address Masking */
>> I'd like to note that we could long have had this if my long-pending emulator
>> patch had gone in at some point.
> Actually what I further have there, and what in the context of patch 15 I
> notice you should have here is
>
> --- a/xen/tools/gen-cpuid.py
> +++ b/xen/tools/gen-cpuid.py
> @@ -278,7 +278,8 @@ def crunch_numbers(state):
>          # superpages, PCID and PKU are only available in 4 level paging.
>          # NO_LMSL indicates the absense of Long Mode Segment Limits, which
>          # have been dropped in hardware.
> -        LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, 
> CMPCCXADD],
> +        LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, CMPCCXADD,
> +             LKGS],
>  
>          # AMD K6-2+ and K6-III processors shipped with 3DNow+, beyond the
>          # standard 3DNow in the earlier K6 processors.
> @@ -347,6 +348,9 @@ def crunch_numbers(state):
>          # computational instructions.  All further AMX features are built on 
> top
>          # of AMX-TILE.
>          AMX_TILE: [AMX_BF16, AMX_INT8, AMX_FP16, AMX_COMPLEX],
> +
> +        # FRED builds on the LKGS instruction.
> +        LKGS: [FRED],
>      }
>  
>      deep_features = tuple(sorted(deps.keys()))

Hmm.  Yes, but normally this is part of guest enablement.

Having now done the Xen work and concluded that we don't actually need
LKGS, I'm rethinking the linkage here.  It's probably the right thing to
do in practice, but probably needs a bit more in the way of
justification.  "built on" doesn't quite cut it IMO.

~Andrew

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