On 14/08/2025 12:20 pm, Jan Beulich wrote: > On 08.08.2025 22:23, Andrew Cooper wrote: >> Of note, CR4.FRED is bit 32 and cannot enabled outside of 64bit mode. >> >> Most supported toolchains don't understand the FRED instructions yet. ERETU >> and ERETS are easy to wrap (they encoded as REPZ/REPNE CLAC), while LKGS is >> more complicated and deferred for now. >> >> I have intentionally named the FRED MSRs differently to the spec. In the >> spec, the stack pointer names alias the TSS fields of the same name, despite >> very different semantics. >> >> Signed-off-by: Andrew Cooper <andrew.coop...@citrix.com> > Acked-by: Jan Beulich <jbeul...@suse.com>
Thanks. >> --- a/xen/arch/x86/include/asm/x86-defns.h >> +++ b/xen/arch/x86/include/asm/x86-defns.h >> @@ -75,6 +75,7 @@ >> #define X86_CR4_PKE 0x00400000 /* enable PKE */ >> #define X86_CR4_CET 0x00800000 /* Control-flow Enforcement >> Technology */ >> #define X86_CR4_PKS 0x01000000 /* Protection Key Supervisor */ >> +#define X86_CR4_FRED 0x100000000 /* Fast Return and Event Delivery */ > ... a UL suffix added here for Misra. I was surprised, but Eclair is entirely fine with this. ~Andrew
