Similar to the other other AlderLake platforms, the C1 and C1E states on ADL-N are mutually exclusive. Only one of them can be enabled at a time.
C1E is preferred on ADL-N for better energy efficiency. C6S is also supported on this platform. Its latency is far bigger than C6, but really close to C8 (PC8), thus it is not exposed as a separate state. Suggested-by: Baieswara Reddy Sagili <baieswara.reddy.sag...@intel.com> Suggested-by: Vinay Kumar <vinay.ku...@intel.com> Signed-off-by: Zhang Rui <rui.zh...@intel.com> [ rjw: Changelog edits ] Signed-off-by: Rafael J. Wysocki <rafael.j.wyso...@intel.com> Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 65c0c2367e9e x86/cpu: Fix Gracemont uarch Alderlake N is an E-core only product using Gracemont micro-architecture. It fits the pre-existing naming scheme perfectly fine, adhere to it. Signed-off-by: Peter Zijlstra (Intel) <pet...@infradead.org> Acked-by: Rafael J. Wysocki <rafael.j.wyso...@intel.com> Acked-by: Hans de Goede <hdego...@redhat.com> Link: https://lore.kernel.org/r/20230807150405.686834...@infradead.org Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 882cdb06b668 Signed-off-by: Jan Beulich <jbeul...@suse.com> --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -678,6 +678,40 @@ static struct cpuidle_state __ro_after_i {} }; +static const struct cpuidle_state gmt_cstates[] = { + { + .name = "C1", + .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_DISABLED, + .exit_latency = 1, + .target_residency = 1, + }, + { + .name = "C1E", + .flags = MWAIT2flg(0x01), + .exit_latency = 2, + .target_residency = 4, + }, + { + .name = "C6", + .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 195, + .target_residency = 585, + }, + { + .name = "C8", + .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 260, + .target_residency = 1040, + }, + { + .name = "C10", + .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 660, + .target_residency = 1980, + }, + {} +}; + static struct cpuidle_state __ro_after_init spr_cstates[] = { { .name = "C1", @@ -1083,6 +1117,10 @@ static struct idle_cpu __ro_after_init i .state_table = adl_l_cstates, }; +static const struct idle_cpu idle_cpu_gmt = { + .state_table = gmt_cstates, +}; + static const struct idle_cpu idle_cpu_spr = { .state_table = spr_cstates, .c1e_promotion = C1E_PROMOTION_DISABLE, @@ -1148,6 +1186,7 @@ static const struct x86_cpu_id intel_idl ICPU(ICELAKE_D, icx), ICPU(ALDERLAKE, adl), ICPU(ALDERLAKE_L, adl_l), + ICPU(ATOM_GRACEMONT, gmt), ICPU(SAPPHIRERAPIDS_X, spr), ICPU(ATOM_GOLDMONT, bxt), ICPU(ATOM_GOLDMONT_PLUS, bxt), @@ -1386,6 +1425,7 @@ static void __init mwait_idle_state_tabl break; case INTEL_FAM6_ALDERLAKE: case INTEL_FAM6_ALDERLAKE_L: + case INTEL_FAM6_ATOM_GRACEMONT: adl_idle_state_table_update(); break; }
