Emerald Rapids (EMR) is the next Intel Xeon processor after Sapphire
Rapids (SPR).
EMR C-states are the same as SPR C-states, and we expect that EMR
C-state characteristics (latency and target residency) will be the
same as in SPR. Therefore, add EMR support by using SPR C-states table.
Signed-off-by: Artem Bityutskiy <artem.bityuts...@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wyso...@intel.com>
Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
74528edfbc66
Signed-off-by: Jan Beulich <jbeul...@suse.com>
--- a/xen/arch/x86/cpu/mwait-idle.c
+++ b/xen/arch/x86/cpu/mwait-idle.c
@@ -1188,6 +1188,7 @@ static const struct x86_cpu_id intel_idl
ICPU(ALDERLAKE_L, adl_l),
ICPU(ATOM_GRACEMONT, gmt),
ICPU(SAPPHIRERAPIDS_X, spr),
+ ICPU(EMERALDRAPIDS_X, spr),
ICPU(ATOM_GOLDMONT, bxt),
ICPU(ATOM_GOLDMONT_PLUS, bxt),
ICPU(ATOM_GOLDMONT_D, dnv),
@@ -1421,6 +1422,7 @@ static void __init mwait_idle_state_tabl
skx_idle_state_table_update();
break;
case INTEL_FAM6_SAPPHIRERAPIDS_X:
+ case INTEL_FAM6_EMERALDRAPIDS_X:
spr_idle_state_table_update();
break;
case INTEL_FAM6_ALDERLAKE:
