[PATCH 5/9] x86/mwait-idle: add Grand Ridge SoC support

[Jan Beulich]

Add Intel Grand Ridge SoC C-states, which are C1, C1E, and C6S.

The Grand Ridge SoC is built with modules, each module includes 4 cores
(Crestmont microarchitecture). There is one L2 cache per module, shared
between the 4 cores.

There is no core C6 state, but there is C6S state, which has module
scope: when all 4 cores request C6S, the entire module (4 cores + L2
cache) enters the low power state.

Package C6 is not supported by Grand Ridge SoC.

Signed-off-by: Artem Bityutskiy <artem.bityuts...@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wyso...@intel.com>
Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 
ac89d11b93cc
Signed-off-by: Jan Beulich <jbeul...@suse.com>

--- a/xen/arch/x86/cpu/mwait-idle.c
+++ b/xen/arch/x86/cpu/mwait-idle.c
@@ -928,6 +928,28 @@ static const struct cpuidle_state snr_cs
        {}
 };
 
+static const struct cpuidle_state grr_cstates[] = {
+       {
+               .name = "C1",
+               .flags = MWAIT2flg(0x00),
+               .exit_latency = 1,
+               .target_residency = 1,
+       },
+       {
+               .name = "C1E",
+               .flags = MWAIT2flg(0x01),
+               .exit_latency = 2,
+               .target_residency = 10,
+       },
+       {
+               .name = "C6S",
+               .flags = MWAIT2flg(0x22) | CPUIDLE_FLAG_TLB_FLUSHED,
+               .exit_latency = 140,
+               .target_residency = 500,
+       },
+       {}
+};
+
 static void cf_check mwait_idle(void)
 {
        unsigned int cpu = smp_processor_id();
@@ -1172,6 +1194,11 @@ static const struct idle_cpu idle_cpu_sn
        .c1e_promotion = C1E_PROMOTION_DISABLE,
 };
 
+static const struct idle_cpu idle_cpu_grr = {
+       .state_table = grr_cstates,
+       .c1e_promotion = C1E_PROMOTION_DISABLE,
+};
+
 #define ICPU(model, cpu) \
        { X86_VENDOR_INTEL, 6, INTEL_FAM6_ ## model, X86_FEATURE_ALWAYS, \
          &idle_cpu_ ## cpu}
@@ -1220,6 +1247,7 @@ static const struct x86_cpu_id intel_idl
        ICPU(ATOM_GOLDMONT_PLUS,        bxt),
        ICPU(ATOM_GOLDMONT_D,           dnv),
        ICPU(ATOM_TREMONT_D,            snr),
+       ICPU(ATOM_CRESTMONT,            grr),
        {}
 };