On 07.04.2025 11:10, Teddy Astie wrote: > --- a/xen/include/public/arch-x86/cpufeatureset.h > +++ b/xen/include/public/arch-x86/cpufeatureset.h > @@ -170,6 +170,7 @@ XEN_CPUFEATURE(SKINIT, 3*32+12) /* SKINIT/STGI > instructions */ > XEN_CPUFEATURE(WDT, 3*32+13) /* Watchdog timer */ > XEN_CPUFEATURE(LWP, 3*32+15) /* Light Weight Profiling */ > XEN_CPUFEATURE(FMA4, 3*32+16) /*A 4 operands MAC instructions */ > +XEN_CPUFEATURE(TCE, 3*32+17) /*H Translation Cache Extension > support */
I consider this too limiting; this is a performance hint only, after all, not affecting correctness when ignored if set. A shadow guest is fine to enable TCE if it sees fit. It'll benefit if later migrated to a HAP- capable host. Further a HAP guest is also fine to set this bit even on a TCE-incapable host. It'll benefit when migrated to a TCE-capable one. What we'd need to ensure is that on TCE-incapable hosts only the guest view of EFER has the bit set, while what's in the VMCB for hardware to use hasn't. (Arguably support for this can come later, but the shortcoming would want pointing out imo.) Jan
