On 07.04.2025 11:10, Teddy Astie wrote: > AMD Translation Cache Extension is a flag that can be enabled in the EFER MSR > to optimize > some TLB flushes. Expose this flag to guest if supported by hardware. This > flag can be > used by Linux since version 6.14. > > Only expose this feature to HAP-enabled guests. Guests with shadow paging > guests have
Nit: double "guests". > their TLB flush operations intercepted and handled separately, without taking > account > to this flag. PV guest follows Xen TLB flush behavior. Commit messages want to have their lines limited to like 75 chars, to cover for e.g. "git log" behavior combined with the general 80 chars line length limit. > --- a/CHANGELOG.md > +++ b/CHANGELOG.md > @@ -18,6 +18,7 @@ The format is based on [Keep a > Changelog](https://keepachangelog.com/en/1.0.0/) > - Support PCI passthrough for HVM domUs when dom0 is PVH (note SR-IOV > capability usage is not yet supported on PVH dom0). > - Smoke tests for the FreeBSD Xen builds in Cirrus CI. > + - Guest support for AMD Translation Cache Extension feature. This may want to say HVM or even HAP. > --- a/xen/arch/x86/pv/emul-priv-op.c > +++ b/xen/arch/x86/pv/emul-priv-op.c > @@ -857,8 +857,8 @@ static uint64_t guest_efer(const struct domain *d) > { > uint64_t val; > > - /* Hide unknown bits, and unconditionally hide SVME and AIBRSE from > guests. */ > - val = read_efer() & EFER_KNOWN_MASK & ~(EFER_SVME | EFER_AIBRSE); > + /* Hide unknown bits, and unconditionally hide SVME, TCE and AIBRSE from > guests. */ > + val = read_efer() & EFER_KNOWN_MASK & ~(EFER_SVME | EFER_TCE | > EFER_AIBRSE); Nit: Please respect line length limits when extending lines. Jan
