On 26/02/2025 10:45 am, Oleksii Kurochko wrote: > Signed-off-by: Oleksii Kurochko <oleksii.kuroc...@gmail.com> > --- > Changes in v2: > - Drop "Support device passthrough when dom0 is PVH on Xen" from > CHANGELOD.md becuase it isn't really ready: > > https://lore.kernel.org/xen-devel/31db7d34-3338-4d88-8721-f2cd4b68f...@gmail.com/T/#m725b559864e5ed6163b59a088b437aa10c36ff16 > --- > CHANGELOG.md | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/CHANGELOG.md b/CHANGELOG.md > index 1979166820..5f5a40855a 100644 > --- a/CHANGELOG.md > +++ b/CHANGELOG.md > @@ -18,6 +18,11 @@ The format is based on [Keep a > Changelog](https://keepachangelog.com/en/1.0.0/) > - Fixed blkif protocol specification for sector sizes different than 512b. > - The dombuilder in libxenguest no longer un-gzips secondary modules, > instead > leaving this to the guest kernel to do in guest context. > + - Reduce xenstore library dependencies.
What is this in reference to? I don't think all of Juergen's series has been merged yet. > + - On Arm: > + - Several FF-A support improvements: add indirect messages support, > transmit > + RXTX buffer to the SPMC, fix version negotication and partition > information > + retrieval. > - On x86: > - Prefer ACPI reboot over UEFI ResetSystem() run time service call. > - Prefer CMOS over EFI_GET_TIME as time source. > @@ -25,6 +30,7 @@ The format is based on [Keep a > Changelog](https://keepachangelog.com/en/1.0.0/) > interrupts instead of logical destination mode. > > ### Added > + - Enable CONFIG_UBSAN (Arm, x86, RISC-V) for GitLab CI. +PPC (just backported that). Also, best to say ARM64, because ARM32 is pending the list.h fix which we deemed too invasive. > - On Arm: > - Experimental support for Armv8-R. > - Support for NXP S32G3 Processors Family and NXP LINFlexD UART driver. > @@ -34,6 +40,9 @@ The format is based on [Keep a > Changelog](https://keepachangelog.com/en/1.0.0/) > - On x86: > - xl suspend/resume subcommands. > - `wallclock` command line option to select time source. > + - Add Support for Paging-Write Feature. (Just so all my feedback is in one place), "Intel EPT". The average person reading these notes isn't enough of an x86 expert to equate EPT with Intel. > + - Zen5 support (including new hardware support to mitigate the SRSO > + speculative vulnerability). AMD Zen5. Again, the target audience aren't all experts. Although, I'd phrase that as "support, including" without brackets. ~Andrew
