Hello,
There were a couple of issues with GICv3 ITS implementation in
Xen. From user perspective it looks like no interrupts are
delivered. I observed those issues when experimented with SR-IOV on
Renesas S4 board. In my case it wasn't a 100% reproducible issue, so
it took some time and couple of tries to fix it. I wasn't sure if my
fix addressed some hardware quirks of S4 board or it was a generic
solution, so I postponed publishing of it.
Later, Stewart Hildebrand had very simmilar issues with his setup. I
shared those 3 patches with him and they fixed his issue as well. So,
I believe we need those changes in Xen mainline.
Second patch ("ARM: GICv3 ITS: do not invalidate memory while sending
a command") is not strictly required, as it just provides a small
optimization, but I believe it would be nice to have it in the code
base.
Volodymyr Babchuk (3):
ARM: GICv3 ITS: issue INVALL command after mapping host events
ARM: GICv3 ITS: do not invalidate memory while sending a command
ARM: GICv3 ITS: flush all buffers, not just command queue
xen/arch/arm/gic-v3-its.c | 27 ++++++++++++++++++++++-----
xen/arch/arm/include/asm/gic_v3_its.h | 2 +-
2 files changed, 23 insertions(+), 6 deletions(-)
--
2.42.0
