>>> On 12.12.16 at 12:40, <luwei.k...@intel.com> wrote: >> >>> On 12.12.16 at 11:35, <luwei.k...@intel.com> wrote: >> > If a counter happend overflow just clear corresponding bit of >> > IA32_PERF_GLOBAL_OVF_CTRL, rather than clear all the bit of this msr. >> >> The code change is fine, but the description appears to be wrong: >> Isn't the change to avoid bits getting wrongly set, rather than any getting >> wrongly cleared? >> > just set the corresponding bits of which counter happened overflow, rather > than set all the available bits of IA32_PERF_GLOBAL_OVF_CTRL when happened > pmu interrupt. > Or > Remove the redundant bits set of IA32_PERF_GLOBAL_OVF_CTRL.
The former seems better to me. Jan _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org https://lists.xen.org/xen-devel
