Name "iss" in this case was used not exactly correctly, because this
is only part of HSR.ISS field. ARM refence manual denotes this
part of ISS as RES0 when it describes encoding for conditional
exceptions.
Signed-off-by: Volodymyr Babchuk <volodymyr_babc...@epam.com>
---
xen/include/asm-arm/processor.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 855ded1..f640d54 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -434,7 +434,7 @@ union hsr {
/* Common to all conditional exception classes (0x0N, except 0x00). */
struct hsr_cond {
- unsigned long iss:20; /* Instruction Specific Syndrome */
+ unsigned long res0:20; /* Reserved */
unsigned long cc:4; /* Condition Code */
unsigned long ccvalid:1;/* CC Valid */
unsigned long len:1; /* Instruction length */
--
2.7.4
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