Wade, Thanks for the feedback. I was able to get what I wanted done by taking another look at the axi_ram_fifo block. UHD seems to provide endless examples for all my problems, I just need the will to seek them. I ended up taking the axis_width_conv() module from the axi_ram_fifo block and using it, and it did exactly what I needed!
My original problem was doing a clock domain crossing from the AXI-stream data to my AXI memory interface (and back) which would need to run at mem_clk as you said. I was constrained by my HLS module being limited to one clock, so I couldn't use HLS to cheat around the HDL like I usually do. This led me on a long rabbit hole of reading Xilinx IP, realizing my original request was improbable, and then finding the correct solution. I did learn alot about how much I don't like the IP GUI though. Thanks, David On Sun, Apr 27, 2025 at 5:31 PM Wade Fife <wade.f...@ettus.com> wrote: > Hi David, > > It is possible, but it can't be done from within RFNoC. The memory > interface logic and clocking live outside of RFNoC. And you have to use the > mem_clk to talk to this logic. The clock that's used for the memory is > provided by the memory interface IP, so the easiest way to change it would > be by modifying that IP in the Vivado MIG GUI. It's the IP located in > fpga/usrp3/top/x300/ip/ddr3_32bit/ddr3_32bit.xci. > > That being said, I can't think of a reason why you would want the memory > interface clock to match the radio clock, since both the radio and the > replay block use the rfnoc_chdr_clk to send/receive data. Perhaps you could > share why you want to change the memory speed? > > Thanks, > > Wade > > On Thu, Apr 24, 2025 at 4:55 PM David <vitishlsfa...@gmail.com> wrote: > >> Hello all, >> >> I would like to know if it's possible to change the X310 DRAM clock >> frequency. My current understanding is that it runs at 300MHz, and I want >> to run it at 200MHz (same as the master clock). >> >> When reviewing default image_core.yml and the replay/axi_dma_fifo blocks, >> I can see that the clock domains are connected with: >> >> x310_HG_rfnoc_image_core.yml: >> >> [image: image.png] >> >> replay.yml: >> >> [image: image.png] >> >> >> Is it as simple as changing the mem clk_domain to ce? Where are the clock >> definitions for _device_? >> >> Thanks, >> >> David >> _______________________________________________ >> USRP-users mailing list -- usrp-users@lists.ettus.com >> To unsubscribe send an email to usrp-users-le...@lists.ettus.com >> >
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