Removing the RFNoC block from the YAML file is the correct move. Is it
possible that when you ran rfnoc_image_builder after modifying the YAML
that it picked up the wrong file?
--M
On Tue, Apr 22, 2025 at 9:17 PM sp <stackprogra...@gmail.com> wrote:
> When i removed rfnoc block in YML file USRP FPGA image, it is not released
> resources for rfnoc block.My question is how can release some resource on
> FPGA in USRP image with removing some extra RFNOC block like DUC or DCC.
> Why remove rfnoc block on YML file don't have any effect on reducing FPGA
> resource!!
>
> Thanks in advance
>
> # General parameters
> # -----------------------------------------
> schema: rfnoc_imagebuilder_args # Identifier for the schema used to
> validate this file
> copyright: 'Ettus Research, A National Instruments Brand' # Copyright
> information used in file headers
> license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License
> information used in file headers
> version: '1.0' # File version
> rfnoc_version: '1.0' # RFNoC protocol version
> chdr_width: 64 # Bit width of the CHDR bus for this image
> device: 'x300'
> default_target: 'X300_HG'
>
> # A list of all stream endpoints in design
> # ----------------------------------------
> stream_endpoints:
> ep0: # Stream endpoint name
> ctrl: True # Endpoint passes control traffic
> data: True # Endpoint passes data traffic
> buff_size: 32768 # Ingress buffer size for data
> ep1: # Stream endpoint name
> ctrl: False # Endpoint passes control traffic
> data: True # Endpoint passes data traffic
> buff_size: 0 # Ingress buffer size for data
> ep2: # Stream endpoint name
> ctrl: False # Endpoint passes control traffic
> data: True # Endpoint passes data traffic
> buff_size: 32768 # Ingress buffer size for data
> ep3: # Stream endpoint name
> ctrl: False # Endpoint passes control traffic
> data: True # Endpoint passes data traffic
> buff_size: 0 # Ingress buffer size for data
> ep4: # Stream endpoint name
> ctrl: False # Endpoint passes control traffic
> data: True # Endpoint passes data traffic
> buff_size: 4096 # Ingress buffer size for data
> ep5: # Stream endpoint name
> ctrl: False # Endpoint passes control traffic
> data: True # Endpoint passes data traffic
> buff_size: 4096 # Ingress buffer size for data
>
> # A list of all NoC blocks in design
> # ----------------------------------
> noc_blocks:
> duc0: # NoC block name
> block_desc: 'duc.yml' # Block device descriptor file
> parameters:
> NUM_PORTS: 1
> ddc0:
> block_desc: 'ddc.yml'
> parameters:
> NUM_PORTS: 2
> radio0:
> block_desc: 'radio_2x64.yml'
> duc1:
> block_desc: 'duc.yml'
> parameters:
> NUM_PORTS: 1
> ddc1:# General parameters
> # -----------------------------------------
> schema: rfnoc_imagebuilder_args # Identifier for the schema used
> to validate this file
> copyright: 'Ettus Research, A National Instruments Brand' # Copyright
> information used in file headers
> license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License
> information used in file headers
> version: '1.0' # File version
> rfnoc_version: '1.0' # RFNoC protocol version
> chdr_width: 64 # Bit width of the CHDR bus for
> this image
> device: 'x300'
> default_target: 'X300_HG'
>
> # A list of all stream endpoints in design
> # ----------------------------------------
> stream_endpoints:
> ep0: # Stream endpoint name
> ctrl: True # Endpoint passes control traffic
> data: True # Endpoint passes data traffic
> buff_size: 32768 # Ingress buffer size for data
> ep1: # Stream endpoint name
> ctrl: False # Endpoint passes control traffic
> data: True # Endpoint passes data traffic
> buff_size: 0 # Ingress buffer size for data
> ep2: # Stream endpoint name
> ctrl: False # Endpoint passes control traffic
> data: True # Endpoint passes data traffic
> buff_size: 32768 # Ingress buffer size for data
> ep3: # Stream endpoint name
> ctrl: False # Endpoint passes control traffic
> data: True # Endpoint passes data traffic
> buff_size: 0 # Ingress buffer size for data
> ep4: # Stream endpoint name
> ctrl: False # Endpoint passes control traffic
> data: True # Endpoint passes data traffic
> buff_size: 4096 # Ingress buffer size for data
> ep5: # Stream endpoint name
> ctrl: False # Endpoint passes control traffic
> data: True # Endpoint passes data traffic
> buff_size: 4096 # Ingress buffer size for data
>
> # A list of all NoC blocks in design
> # ----------------------------------
> noc_blocks:
> duc0: # NoC block name
> block_desc: 'duc.yml' # Block device descriptor file
> parameters:
> NUM_PORTS: 1
> ddc0:
> block_desc: 'ddc.yml'
> parameters:
> NUM_PORTS: 2
> radio0:
> block_desc: 'radio_2x64.yml'
> duc1:
> block_desc: 'duc.yml'
> parameters:
> NUM_PORTS: 1
> ddc1:
> block_desc: 'ddc.yml'
> parameters:
> NUM_PORTS: 2
> radio1:
> block_desc: 'radio_2x64.yml'
> replay0:
> block_desc: 'replay.yml'
> parameters:
> NUM_PORTS: 2
> MEM_ADDR_W: 30
>
> # A list of all static connections in design
> # ------------------------------------------
> # Format: A list of connection maps (list of key-value pairs) with the
> following keys
> # - srcblk = Source block to connect
> # - srcport = Port on the source block to connect
> # - dstblk = Destination block to connect
> # - dstport = Port on the destination block to connect
> connections:
> # ep0 to radio0(0) - RFA TX
> - { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 }
> - { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 }
> # radio(0) to ep0 - RFA RX
> - { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 }
> - { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 }
> # radio0(1) to ep1 - RFA RX
> - { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 }
> - { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 }
> # ep2 to radio1(0) - RFA TX
> - { srcblk: ep2, srcport: out0, dstblk: duc1, dstport: in_0 }
> - { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 }
> # radio1(0) to ep2 - RFA RX
> - { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 }
> - { srcblk: ddc1, srcport: out_0, dstblk: ep2, dstport: in0 }
> # radio0(1) to ep3 - RFA RX
> - { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 }
> - { srcblk: ddc1, srcport: out_1, dstblk: ep3, dstport: in0 }
> # ep4 to replay0(0)
> - { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
> # replay0(0) to ep4
> - { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
> # ep5 to replay0(1)
> - { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
> # replay0(1) to ep5
> - { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
> # BSP Connections
> - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport:
> ctrlport_radio0 }
> - { srcblk: radio1, srcport: ctrl_port, dstblk: _device_, dstport:
> ctrlport_radio1 }
> - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
> - { srcblk: _device_, srcport: x300_radio0, dstblk: radio0, dstport:
> x300_radio }
> - { srcblk: _device_, srcport: x300_radio1, dstblk: radio1, dstport:
> x300_radio }
> - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport:
> time_keeper }
> - { srcblk: _device_, srcport: time_keeper, dstblk: radio1, dstport:
> time_keeper }
>
> # A list of all clock domain connections in design
> # ------------------------------------------
> # Format: A list of connection maps (list of key-value pairs) with the
> following keys
> # - srcblk = Source block to connect (Always "_device"_)
> # - srcport = Clock domain on the source block to connect
> # - dstblk = Destination block to connect
> # - dstport = Clock domain on the destination block to connect
> clk_domains:
> - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
> - { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
> - { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce }
> - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
> - { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
> - { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce }
> - { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
> block_desc: 'ddc.yml'
> parameters:
> NUM_PORTS: 2
> radio1:
> block_desc: 'radio_2x64.yml'
> replay0:
> block_desc: 'replay.yml'
> parameters:
> NUM_PORTS: 2
> MEM_ADDR_W: 30
>
> # A list of all static connections in design
> # ------------------------------------------
> # Format: A list of connection maps (list of key-value pairs) with the
> following keys
> # - srcblk = Source block to connect
> # - srcport = Port on the source block to connect
> # - dstblk = Destination block to connect
> # - dstport = Port on the destination block to connect
> connections:
> # ep0 to radio0(0) - RFA TX
> - { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 }
> - { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 }
> # radio(0) to ep0 - RFA RX
> - { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 }
> - { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 }
> # radio0(1) to ep1 - RFA RX
> - { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 }
> - { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 }
> # ep2 to radio1(0) - RFA TX
> - { srcblk: ep2, srcport: out0, dstblk: duc1, dstport: in_0 }
> - { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 }
> # radio1(0) to ep2 - RFA RX
> - { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 }
> - { srcblk: ddc1, srcport: out_0, dstblk: ep2, dstport: in0 }
> # radio0(1) to ep3 - RFA RX
> - { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 }
> - { srcblk: ddc1, srcport: out_1, dstblk: ep3, dstport: in0 }
> # ep4 to replay0(0)
> - { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
> # replay0(0) to ep4
> - { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
> # ep5 to replay0(1)
> - { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
> # replay0(1) to ep5
> - { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
> # BSP Connections
> - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport:
> ctrlport_radio0 }
> - { srcblk: radio1, srcport: ctrl_port, dstblk: _device_, dstport:
> ctrlport_radio1 }
> - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
> - { srcblk: _device_, srcport: x300_radio0, dstblk: radio0, dstport:
> x300_radio }
> - { srcblk: _device_, srcport: x300_radio1, dstblk: radio1, dstport:
> x300_radio }
> - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport:
> time_keeper }
> - { srcblk: _device_, srcport: time_keeper, dstblk: radio1, dstport:
> time_keeper }
>
> # A list of all clock domain connections in design
> # ------------------------------------------
> # Format: A list of connection maps (list of key-value pairs) with the
> following keys
> # - srcblk = Source block to connect (Always "_device"_)
> # - srcport = Clock domain on the source block to connect
> # - dstblk = Destination block to connect
> # - dstport = Clock domain on the destination block to connect
> clk_domains:
> - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
> - { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
> - { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce }
> - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
> - { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
> - { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce }
> - { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
>
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