[USRP-users] Re: rfnoc_modtool io_ports not being populated

[Philipp Niedermayer]

It's a known issue from the time the tool was still called "rfnoc_create_verilog" (but using the same templates).

See https://github.com/EttusResearch/uhd/issues/605



*From:* Brian Padalino <bpadal...@gmail.com>

*Sent:* Tuesday, 11 March 2025 at 21:47

*To:* USRP-users@lists.ettus.com <usrp-users@lists.ettus.com>

*Subject:* [USRP-users] rfnoc_modtool io_ports not being populated

Quote: "You did the right thing. The io_ports aren't currently supported by rfnoc_create_verilog, so AXI ports have to be added manually."

I am trying to add a timekeeper listener, axi_mm memory interface, and a pps interface using rfnoc_modtool with the yml description and it doesn't seem like it actually adds the ports to the top level when the code is being generated.

Is this a known issue? Am I doing something wrong?

Sorry for the confusion.

Thanks,
Brian

_______________________________________________
USRP-users mailing list --usrp-users@lists.ettus.com
To unsubscribe send an email tousrp-users-le...@lists.ettus.com

I verified this by using the replay.yml block in an OOT and it only seems to create the chdr, ctrl, and adds the mem_clk input.

smime.p7s
Description: Kryptografische S/MIME-Signatur

_______________________________________________
USRP-users mailing list -- usrp-users@lists.ettus.com
To unsubscribe send an email to usrp-users-le...@lists.ettus.com