Hello, \ \ I am currently facing an issue with ADC saturation on a USRP X310 equipped with a UBX daughterboard. We are conducting measurements using an LTE signal and a sinusoidal input signal, but it seems that the ADC is saturating, leading to a loss of dynamic range in our measurements.
Test context: \ We are transmitting (using a generator) an LTE signal with a power of -50 dBm at a center frequency of 1815 MHz. Then, we add a sinusoidal signal at 1865 MHz with a power of -30 dBm. This second, more powerful signal seems to be causing the ADC to saturate, even though we don’t see it directly in the IQ samples due to the digital filtering applied downstream. \ \ Problem: \ We suspect that the ADC saturation occurs before IQ conversion and is therefore masked by the digital filters. This results in a loss of dynamic range in our measurements, and we feel that adjusting the gain based on the IQ samples may not be reliable. \ \ Question: \ How can this ADC saturation be detected upstream of the IQ processing? Are there tools or methods to directly monitor the sample values at the output of the ADC in the USRP (before digital filtering) to prevent saturation? \ Do you have any advice for implementing an automatic gain controller (AGC) based on reliable saturation indicators? \ We would appreciate any suggestions or experiences in resolving this issue. If you have encountered a similar problem or have ideas on how to address it, we would be happy to hear your recommendations. Thank you very much for your help!
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