OK. So, the error you get with "uhd_image_loader" is caused by a "bad build" that occurs if the option DRAM=1 is not included when using the Replay block. I do not know why that the build itself does not fail, but that is the case. Thus, you still don't have a valid FPGA build for the E310 with the Replay block.
For the YML file that I sent, the compatibility with UHD version should be fixable with minimal changes. Attached is a new file which updates the name of the radio block. Give this a try. If it doesn't work, see if you can notice anything obvious that is preventing it from running. Rob On Tue, Dec 19, 2023 at 5:07 AM <engr.muhd.has...@gmail.com> wrote: > Dear Rob, > > You are right, when I try to run this command “rfnoc_image_builder -y > ./e310_rfnoc_image_core.yml”, *it fails*. *I also tried to use your given > YML file*, it was not successful because of the different UHD version. > The only command which worked for me is “rfnoc_image_builder -y > ./e310_rfnoc_image_core.yml -t E310_SG3 --fpga-dir ~/uhd/fpga/”. > > Moreover I noticed that the bit file from the build folder is the actual > file which I have to use. But I get error which I discussed earlier. > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
e310_replay_image_core.yml
Description: Binary data
_______________________________________________ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com