Hi Wade & Rob, Thank you for your help.
I am a new user, so I do not know much about Linux and FPGA. My aim is to use my usrp with high sampling rate so I was recommended to use RFNoC replay block. For this purpose, I received YML file from Ettus (from Jonathon). I replaced that file (e310_rfnoc_image_core.yml) with the already existing file to the location (/uhd/fpga/usrp3/top/e31x) and from this folder I executed the command “rfnoc_image_builder -y\ ./e310_rfnoc_image_core.yml “. I am not sure whether I did it correctly or not. regards Hassan
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