On 07/06/2023 06:20, Kevin Williams wrote:
Hi,
Why can't this be fixed in the USRP builds by upgrading to 2021.2
which apparently has addressed this fault?
I have added a trivial delay and my image now builds in 2021.1 after
many failures while trying to develop. It is random, and I waste an
hour or two almost every day because of this.
I do not have time for this random approach to building firmware.
Not addressing this particular issue, but FPGA place-and-route is an
inherently random process that uses
random placement and then tries to successively optimize that
placement to make timing "work". That is
why it takes so long, and why sometimes, when I've worked with FPGA
folks, when timing won't close, they
just ran the build again, hoping for a different random outcome.
This is one of the reasons I never got much into FPGA design myself--the
build process is non-deterministic.
Regards, Kevin
--
Kevin Williams, Ph.D.
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