On 27/04/2023 14:54, Tillson, Bob (US) via USRP-users wrote:
Thanks for the response Marcus.
This looks like it is converting the wire format to the host format.
I was wondering about a bit before that when the A2D delivers to the
FPGA if there was any logic within that performed any mapping (lets
assume I asked for sc16 samples with a 12 bit A2D)…
The other Marcus also brought up that there is some futzing going on
as well because typically the A2D sees more BW than the requested
sample rate, etc…
My guess is every radio is different and you need to get into the
nickers of the firmware/A2D interface to understand exactly what is
going on…
Well, to a first order, yes, every radio is different.
But in the USRP space, the A2D resolution is converted to a standardized
"wire format" before being sent to the host.
The host library then takes that and converts it into the desired
host format.
The samples coming out of the ADC are usually filtered and down-sampled
using a DDC (Digital Downconverter) that
provides a bandwidth towards the host that is generally alias-free at
the programmed sample rate.
Yes, the ADC nearly always "sees" more bandwidth than the desired sample
rate, but there's generally enough dynamic
range that the DDC filters can still produce a quality down-sampled
product towards the host.
Most USRP configurations are arranged so that the analog bandwidth ahead
of the ADC is at about 80% or less of
the relevant Nyquist bandwidth for the ADC rate.
Most applications don't really need to care about the details. You ask
for a given sample-rate (subject to the
sample-rates available on that particular hardware) and the USRP
delivers that as a "clean" complex-sampled
bandwidth.
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