Thanks for the response Marcus.

This looks like it is converting the wire format to the host format.

I was wondering about a bit before that when the A2D delivers to the FPGA if 
there was any logic within that performed any mapping (lets assume I asked for 
sc16 samples with a 12 bit A2D)…

The other Marcus also brought up that there is some futzing going on as well 
because typically the A2D sees more BW than the requested sample rate, etc…

My guess is every radio is different and you need to get into the nickers of 
the firmware/A2D interface to understand exactly what is going on…

From: Marcus Müller <marcus.muel...@ettus.com>
Sent: Friday, April 21, 2023 8:56 AM
To: usrp-users@lists.ettus.com
Subject: [USRP-users] Re: A2D bit depth vs IQ

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Hi Bob,

there's no saturation flag coming from the hardware.

The conversion is done within UHD running on your host machine, and the source 
files you'd want to look into are all in uhd/host/lib/convert in the UHD source 
code.

Best regards,
Marcus
On 20.04.23 18:34, Tillson, Bob (US) via USRP-users wrote:
Hello peeps,

Just wondering if anyone could point me to where the mapping between bits and 
IQ takes place.

Curious if the strategy is the same across platforms even though bit depth 
varies (b205: 12 bits, X310: 15 bits, N310: 16 bits, X410: 12 bits…).

The above info in general would be useful, what I am really looking to do is 
spot saturation from the IQ only since I don’t know of any other place where 
something
like the saturation flag is passed through.

Any thought would be greatly appreciated.

Thanks,



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