On Wed, Mar 22, 2023 at 10:40 PM Wade Fife <wade.f...@ettus.com> wrote:
> Hi Brian, > > Unfortunately, the DSP inside the current RFNoC DDC block processes one > sample per clock cycle. So the maximum sample rate through the DDC is the > same as the rate of the clock you provide to the ce clock input. With the > 400 MHz bitstreams, radio_2x is 245.76 MHz. Because this is below the > 491.52 Msps input rate, you're getting overflows. > Got it. Thanks for the clarification. So is there a filter instantiated in the BD of the 200 MHz design which does the first initial decimation by 2 that is missing in the 400 MHz image? Also, don't the clocks need to be slightly faster than the sample rate to also include the CHDR header information in stream, or is that handled some other way in the X410 designs? Thanks, Brian
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