Oh yeah, I forgot.  Does this imply that there is no way to keep UHD from
swapping bytes in an rx_streamer (using X310)?  If so, this seems like a
problem for RFNoC development since the data coming across the wire can be
in any format the designer chooses.  And, swapping in the FPGA is not a
good solution because you don't know the Endianness of the host.
Rob

On Wed, Mar 8, 2023 at 12:07 PM Marcus D. Leech <patchvonbr...@gmail.com>
wrote:

> On 08/03/2023 11:42, Rob Kossler wrote:
>
> Maybe can you just change the streamer OTW & CPU format to "sc8" such that
> no byte swapping will occur?
>
> I know that on the default X3xx builds, there's no sc8 format implemented
> on the USRP end.
>
>
>
> On Tue, Mar 7, 2023 at 10:31 PM Wade Fife <wade.f...@ettus.com> wrote:
>
>> You could swap the bytes in your block, or swap them in software on the
>> host. The data gets rearranged by the streamer depending on the data type
>> configured (e.g., sc16) and the endianness of the host machine.
>>
>> Wade
>>
>> On Tue, Mar 7, 2023 at 2:45 AM Vermeulen, Bas (Consultant) via USRP-users
>> <usrp-users@lists.ettus.com> wrote:
>>
>>> Hi,
>>>
>>> We are developing an RFNOC module that takes I/Q data, and turns that
>>> into two 8 bit values.
>>> I have a test program that sends data to the RFNOC module, and receives
>>> the modified data.
>>>
>>> The RFNOC module treats the two 8 bit values as one signed 16 bit value.
>>> When I read the data from the test program, I get it in the wrong order:
>>>
>>> Send: Re0 Im0 Re1 Im1 Re2 Im2 Re3 Im3
>>> Receive: Val1 Val0 Val3 Val2
>>>
>>> Does anyone have any idea how to fix the order of the received values?
>>>
>>> Regards,
>>>
>>> Bas Vermeulen
>>>
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