Greetings, I have 2 USRP front-ends - N210 and N310. I want to develop a GNSS Receiver inside my FGPA - xilinx ZCU102 - and use one of the USRP devices only as the front-end. The receiver is quite large so I need an external board for all the signal processing chain. The receiver has two implementations - software-only & hybrid. In hybrid mode some tasks of the processing chain are accelerated in hardware.
The software-only version of the receiver running on my ZCU102 is able to configure the N210 and read packets over ethernet correctly. However, with the hybrid version of the receiver, I want to read the digital IQ samples from the front end directly in hardware. For example, I am able to do this with the ZCU102 connected to FMComm2/3 using the FMC connection on the FPGA. AD provides HDL reference designs to support communication between multiple front-ends and multiple FPGAs. Is there a similar way to read the digital samples directly in hardware using the N210? The N210 only has the ethernet and a MIMO port. Thanks in advance.
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