On Thu, May 5, 2022 at 11:45 AM Wade Fife <wade.f...@ettus.com> wrote:
> It's a limitation of the FPGA interface to the RFIC. It doesn't support > the tight setup/hold requirements for operation at the higher clock clock > rate required for 2 x 61.44 Msps. > > Wade > This sounds wrong to me unless you have some very serious bus skew in the layout. The clock and data delays built into the AD9361 along with the fact the FPGA is a Zynq-7045 should be enough to get some valid setup/hold times. The LVDS interface is pretty robust and I've seen it work very well on many designs. Can you elaborate more on what the deficiency is with the FPGA interface to the RFIC? Brian
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