Hi, I have a signal processing block that includes a zero-padded FFT (50% zeros) that I built for the N310. Because of the throttling that occurs during insertion of zeros, I expect that my FFT will need to be clocked at a bit more than twice the max sample rate. So, since I want to operate the N310 at the highest sample rate of 125 MS/s, it seems that my FFT will need to be clocked >= 260 MHz. I'm wondering how to do it.
I've looked at the RFNoC specification and my block is already set up to use the "CE" clock for both control & data. In the rfnoc spec, it mentions that I can enter a "range" for my clock in the block definition yaml. But, I also see that in the end, the top N310 yaml will require me to map a _device clock to my block's CE clock port. It's not clear to me how this works. Does it help to provide a range in the block definition yaml? Or, perhaps it is even necessary? How do I specify in the top N310 yaml which device clock will map to my blocks CE clock port? It seems to me that I am missing a step (defining a clock somewhere?). I am pretty much a novice, so I expect that this is the cause of my confusion. I am even struggling to figure out what the current clock rates are (rfnoc_ctrl, rfnoc_chdr, ce, etc) and where they are defined. Any help would be appreciated. Rob
_______________________________________________ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
