On 2022-01-17 09:10, Ivan Zahartchuk wrote:
Sorry to insist, but it is very important for me to know the answer to
the question.
Ivan:
I did NOT see this message on the list when you first posted it, I
apologize.
You mention N210, but NOT the daughtercard involved.
The N210 has had very little new work done on it in the last several
years, and is in "maintenance" mode, so updating to a new UHD version
is unlikely to change any of its inherent properties.
With 8-bit samples over ethernet on N210 you can support 50Msps, which
is half of the total bandwidth you need. My *guess* is that you will
have a very
hard time doing what you need to do with the N210 hardware,
regardless of the daughtercard. The PLL synthesizers just don't lock
that fast.
---------- Forwarded message ---------
От: *Ivan Zahartchuk* <adray0...@gmail.com>
Date: пт, 14 янв. 2022 г. в 18:03
Subject: Enabling fast lock USRP N210.
To: usrp-users <usrp-users@lists.ettus.com>
Hello. I need to simulate a heavy RF environment. It is necessary to
generate a chirp signal in a 100 MHz band with a total speed of one
run of about 300 µs. But I only have USRP N210. In this regard, I have
several questions.
1. Is it possible to enable fast lock using uhd 4 drivers?
2. Is it possible to generate such a structure with such time?
I have a bad relationship with FPGA....
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