Hello. I need to simulate a heavy RF environment. It is necessary to generate a chirp signal in a 100 MHz band with a total speed of one run of about 300 µs. But I only have USRP N210. In this regard, I have several questions. 1. Is it possible to enable fast lock using uhd 4 drivers? 2. Is it possible to generate such a structure with such time? I have a bad relationship with FPGA....
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