You might need to also clear the "build-ip" folder. Can you try running "make cleanall" then try to build it again? I think I saw that error once when I neglected to clean everything. Let me know if that doesn't work.
Also, the default X410 images don't actually use that IP, so you can remove it from the build. Edit fpga/usrp3/top/x400/Makefile.inc and delete the three lines that reference "ddr4_64bits" or "DDR4_64BITS", then it should skip that IP in the build. Wade On Sat, Oct 2, 2021 at 1:04 AM Dario Pennisi <da...@iptronix.com> wrote: > Hi, > i've been trying to compile X410 with no luck. apparently the issue is > with Vivado installation as it's failing the generation of the DDR4 IP > however i made sure i installed the proper version of it, including patches: > > * GNU bash, version 5.0.17(1)-release (x86_64-pc-linux-gnu) > * Python 3.8.10 > * Vivado v2019.1.1_AR73068 (64-bit) > > my machine is running Ubuntu 20.04.1 and is capable of compiling N310 > builds successfully. > > UHD version is 4.1.0.4 (25d617cad7db69fa04699df5f93ece06b0a61199) however > this issue was happening since 4.1.0.0. > > below a dump of the failing bit: > > ======================================================== > BUILDER: Building IP ddr4_64bits > ======================================================== > BUILDER: Staging IP in build directory... > BUILDER: Reserving IP location: > /home/massimo/workdirs/pdc_demod/work/src/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/ddr4_64bits > BUILDER: Retargeting IP to part zynquplusRFSOC/xczu28dr/ffvg1517/-1/e... > BUILDER: Building IP... > [00:00:00] Executing command: vivado -mode batch -source > /home/massimo/workdirs/pdc_demod/work/src/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl > -log ddr4_64bits.log -nojournal > WARNING: [IP_Flow 19-2162] IP 'ddr4_64bits' is locked: > CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the > following file is locked: > /home/massimo/workdirs/pdc_demod/work/src/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/ddr4_64bits/ddr4_64bits.xci > CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the > following file is locked: > /home/massimo/workdirs/pdc_demod/work/src/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/ddr4_64bits/ddr4_64bits.xci > [00:00:07] Current task: Initialization +++ Current Phase: Starting > [00:00:07] Current task: Initialization +++ Current Phase: Finished > [00:00:07] Executing Tcl: synth_design -top ddr4_64bits -part > xczu28dr-ffvg1517-1-e -mode out_of_context > [00:00:07] Starting Synthesis Command > WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products > for Synthesis target. These output products could be required for > synthesis, please generate the output products using the generate_target or > synth_ip command before running synth_design. > WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products > for Implementation target. These output products could be required for > synthesis, please generate the output products using the generate_target or > synth_ip command before running synth_design. > WARNING: [IP_Flow 19-2162] IP 'ddr4_64bits' is locked: > ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources > specified > ERROR: [Common 17-53] User Exception: No open design. Please open an > elaborated, synthesized or implemented design before executing this command. > ERROR: [Common 17-53] User Exception: No open design. Please open an > elaborated, synthesized or implemented design before executing this command. > ERROR: [Common 17-53] User Exception: No open design. Please open an > elaborated, synthesized or implemented design before executing this command. > ERROR: [Common 17-53] User Exception: No open design. Please open an > elaborated, synthesized or implemented design before executing this command. > ERROR: [Common 17-53] User Exception: No open design. Please open an > elaborated, synthesized or implemented design before executing this command. > ERROR: [Common 17-53] User Exception: No open design. Please open an > elaborated, synthesized or implemented design before executing this command. > CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file > '/home/massimo/workdirs/pdc_demod/work/src/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/ddr4_64bits/ddr4_64bits.xml' > CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file > '/home/massimo/workdirs/pdc_demod/work/src/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/ddr4_64bits/ddr4_64bits.xml' > CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file > '/home/massimo/workdirs/pdc_demod/work/src/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/ddr4_64bits/ddr4_64bits.xml' > CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file > '/home/massimo/workdirs/pdc_demod/work/src/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/ddr4_64bits/ddr4_64bits.xml' > CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file > '/home/massimo/workdirs/pdc_demod/work/src/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/ddr4_64bits/ddr4_64bits.xml' > ERROR: [Vivado 12-398] No designs are open > [00:00:07] Current task: Synthesis +++ Current Phase: Starting > [00:00:07] Current task: Synthesis +++ Current Phase: Finished > [00:00:07] Process terminated. Status: Failure > > ======================================================== > Warnings: 4 > Critical Warnings: 7 > Errors: 8 > > since it seems the issue is related to locking i tried serveral times > cleaning up the build directory or even making just X410_IP target with no > success. > any hints on what is currently going wrong? > thanks, > Dario Pennisi > > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
_______________________________________________ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
