On 08/09/2021 02:24 PM, Black, Robert wrote:
Totally agree that it would be complicated, expensive, etc to support
multiple front-end sampling rates. I have seen it done in the past,
but typically in cases where the RF input, preselection, tuning (i.e.
first frequency conversion) was all being done in analog.
rb
To be clear, the X3xx compatible daughterboards are ALL analog. MOST of
them (on the RX path) are complex-baseband conversion, with
some exceptions, like Twinrx, which use a LOW-IF, and the FPGA
converts to a complex-baseband before the end application sees the data.
Frequency synthesis and conversion are all done on-card, and the
ADCs/DACs on the X310 motherboard sample the analog outputs (or inputs
for the TX direction). For direction-conversion cards that provide
analog I/Q, there is typically a fixed elliptic filter with a cut-off
designed to
be optimal for the ADC on the motherboard, which is why several of
the daughtercards are available in -80 and -160 MHz versions which
relate to their analog output bandwidth.
With adequate bit-width on theADC (14-bits in the case of X310),
extra-tight analog filtering ahead of the ADC isn't necessary unless you
have
very very loud close-in interferers that would tend to exceed the
dynamic range of the ADC. There's roughly 80ish dB of dynamic range
in the x310 ADCs, so it isn't usually a problem. Filtering in the
digital domain is nearly always better.
*From:*Marcus D. Leech <patchvonbr...@gmail.com>
*Sent:* Monday, August 9, 2021 1:03 PM
*To:* usrp-users@lists.ettus.com
*Subject:* [USRP-users] Re: X310 RFNoc radio block question
[EXTERNAL EMAIL]
On 08/09/2021 01:35 PM, Brian Padalino wrote:
On Mon, Aug 9, 2021 at 1:21 PM Black, Robert <rbl...@d16.swri.us
<mailto:rbl...@d16.swri.us>> wrote:
Brian yes.- The Radio block is permanently running at a
permanent 200 MSamp rate.
I would actually be useful to be able to change (reduce) the
ADC sampling clock, with appropriate analog anti-aliasing
filtering in front of the device. It is too bad that the radio
hardware cannot be configured to support this.
The ADC clock on the X310 is constrained by timing-closure constraints
in the FPGA from what I understand, which is why it has only a couple of
different rates. But if you made it broadly-flexible, then the
various daughtercards available would dwindle to only those that have
variable analog bandwidth to match the ADC and DAC rate.
When USRPs were first introduced, the ADC ran at a fixed 64Msps rate.
Similarly with USRP2 and USRP N210 at 100Msps. That changed in
some parts of the family tree, but not others.
Many of the daugtercards for X3xx family use discrete
synthesizer+mixer implementations, and it's fairly difficult to design
variable-properties
anti-alias filters that scale over very large bandwidths. The
fixed-converter-rate-with-DUC/DDC-in-FPGA is a pretty normal
architecture, and
it offers considerable advantages over analog-heavy approaches.
Even in RFIC chips like AD9361, the variable-user-bandwidth is mostly
implemented in an embedded DSP engine in the ASIC.
Just curious - why the hesitation on using the DDC block?
The oversampling ratio should actually help you out, unless you
have some really really close-in jammers - but even then would an
analog filter help that much? The linearity of the ADC should be
very good, and digitally filtering should be superior - yes?
Possibly even get some bit-growth with digital filtering and
decimation?
Brian
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