Hi Dario, Could you share the YAML description of the FPGA and your block with me, and maybe the generated rfnoc_image_core Verilog file? I'd like to understand what's going on.
Thanks, Wade On Thu, Jun 24, 2021 at 8:50 AM Dario Pennisi <da...@iptronix.com> wrote: > Hi, > i developed a rfnoc block based on uhd 4.0. this block has two input ports > meant to be connected statically to the two radios and to have a single > output port that is meant to go to the PC. > if i connect the radio0 to in0 and an endpoint to in1 so that i can either > feed data from the PC or from radio1 everything works however if i connect > radio0 to in0 and radio1 to in1 statically gnuradio won't start saying > there's no route to the control port. > I see that the generated verilog file has a control port connection in the > control axi crossbar however for some reason UHD seems not to know how to > reach it. > Is there any possibility to handle the case of connecting everything > statically? i really need to save as many resources as possible in the > final build. > thanks, > > Dario Pennisi > > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
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