On Fri, Jun 4, 2021 at 2:21 AM Viktor Erdelyi <vik...@ist.osaka-u.ac.jp> wrote:
> You're right Marcus, 0.9GHz seems to be better indeed (see image). Also > thanks for the input on the B205 PLL. > > May I ask in what way phase noise can affect the signal's frequency? > According to an NI webpage [1], it "deals with very short time scales and > produces effects that look more like unwanted modulation changing the shape > of the waveform rather than a wandering frequency". Am I missing something? > It should be noted the B205 doesn't really have an analog PLL like the B200/B210/X-series. Check the schematic: https://files.ettus.com/schematics/b200mini/b200mini.pdf The VTCXO is fed by a 16-bit DAC and the FPGA does some counting to try to keep it locked, but it doesn't have the feedback loop that the actual analog PLL does. Kind of comparing apples with oranges at that point. Brian
_______________________________________________ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
