Hi, I developed a custom RFNoC block that implements an FIR filter having complex taps (using 2 instances of Xilinx FIR IP with 2 inputs each). The taps are reloadable via an AXI bus. After implementing a successful testbench, I later discovered an issue when running with UHD and the actual image. The reloaded taps had I/Q swapped. So, I changed my block controller to perform this swap and now things work.
I'm trying to understand if this makes sense or if I have fooled myself. My implementation uses the legacy "axi_settings_reg" to load coefficients on the IPs reload axi input. The register width is 32 and I use the upper 16 bits as the input to the "real" FIR instance and the lower 16 bits as the input to the "imag" FIR instance. When I run the testbench, I get the expected results without needing to swap real/imag. When I run with UHD and the built FPGA image, I must swap the real/imag parts in the block controller in order to get the correct results. I wondered why I did not have to do something similar when streaming I/Q data to my block (or other blocks), but then figured that maybe UHD takes care of such swapping automatically. Is this true? If so, am I going about this the right way by swapping I/Q in the block controller? Why does the testbench work without swapping? Rob
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