Hi Rob,
Thanks for your reply :)
On 21/01/21 09:32, Rob Kossler wrote:
> [...]
> In the rfnoc_rx_to_file program,
> streaming is started by the function rx_stream->issue_stream_cmd(). Note
> that this is a command to the streamer which then must be forwarded to the
> gain controller and then the ddc controller and then the radio controller
> which will then turn on the radio.
I have a question regarding that statement.
Since the gain block and the radio+ddc are on different EP,
wouldn't the rx_streamer able to transfer that command to the radio
without forwarding it to the gain block?
I do not know the type of issue_stream_cmd.
>From the RFNoC Specification, it is stated that it is an "Action",
"calling into API provided by the graph".
It is also stated that it "propagates". But it does not specify
in which case it does or not and how it does it.
> So, one question I have is: does the command make it to the radio? I think
> that you can tell by looking at the LED - does it turn on?
>
> - If so, then I am on the wrong path.
> - If not, then
> - Maybe there is some setting in the gain block controller that is
> not forwarding the command.
> - Or, more likely, maybe the gain block controller is not being used
> at all because of the block finding issue "block#0" vs "gain#0". In
> this
> case, perhaps building the gain block controller in-tree would help
You are right!
The LED does not turn on when putting the gain block
(Radio -> DDC -> Gain -> rx_streamer).
So it seems that the stream_cmd is not forwarded... But why?
You said that I could try to build the controller in-tree.
I would like to avoid that.
Could I issue_stream_cmd on the radio_ctrl instead of rx_streamer?
How would it work with multiple radios (like in the X310)?
On a side note:
Are we forced to implement a custom controller for each RFNoC block?
I was expecting that I could just write the verilog part
and use the basic noc_block_base controller to manage my blocks in C++,
using regs()->peek32/poke32 to set my registers etc.
But from above, it seems that it does not forward the issue_stream_cmd
by default? Is that correct?
> Also, it might help if you turn on "debug" logging (export
> UHD_LOG_LEVEL=debug; export UHD_LOG_CONSOLE_LEVEL=debug) and run the
> rfnoc_rx_to_file example. First try with a working block such as FFT and
> then with the gain block and see if there are any clues.
> Rob
I attached 3 logs:
- normal.log is (Radio -> DDC -> rx_streamer)
- fft.log is (Radio -> DDC -> fft -> rx_streamer)
- gain.log is (Radio -> DDC -> gain -> rx_streamer)
I just had to specify "--spp 256" to match the default FFT size
(otherwise I get overrun).
--
Cédric Hannotier
$ ./test --rate 20e6 --block-id 0/FFT#0 --spp 256 --progress
Creating the RFNoC graph with args: ...
[INFO] [UHD] linux; GNU C++ version 10.2.1 20201224; Boost_107400; UHD_4.0.0.0-4
[DEBUG] [MPMD] Discovering MPM devices on port 49600
[DEBUG] [MPMD] Discovering MPM devices on port 49600
[DEBUG] [MPMD] Discovering MPM devices on port 49600
[INFO] [X300] X300 initialization sequence...
[DEBUG] [X300] Motherboard 0 has remote device ID: 1
[DEBUG] [X300] Setting up basic communication...
[DEBUG] [X300] Using FPGA version: 38.0 git hash: 1a34ba8-dirty
[DEBUG] [X300] Loading values from EEPROM...
[DEBUG] [X300] Determining maximum frame size...
[INFO] [X300] Maximum frame size: 8000 bytes.
[DEBUG] [X300] Setting up RF frontend clocking...
[DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=8, Requested=0.000000,
Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns
[DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=4, Requested=0.000000,
Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns
[DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=5, Requested=0.000000,
Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns
[DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=0, Requested=0.000000,
Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns
[DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=2, Requested=0.000000,
Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns
[INFO] [X300] Radio 1x clock: 200 MHz
[DEBUG] [X300] Motherboard 0 has local device IDs:
[DEBUG] [X300] * 2
[DEBUG] [RFNOC::MGMT] Starting topology discovery from device:2/sep:1
[DEBUG] [RFNOC::MGMT] Discovered node device:1/xport:0
[DEBUG] [RFNOC::MGMT] Initialized node device:1/xport:0
[DEBUG] [RFNOC::MGMT] Discovered node device:1/xbar:0
[DEBUG] [RFNOC::MGMT] Initialized node device:1/xbar:0
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:0
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:0
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:1
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:1
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:2
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:2
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:3
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:3
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:4
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:4
[DEBUG] [RFNOC::MGMT] The following endpoints are reachable from device:2/sep:1
[DEBUG] [RFNOC::MGMT] * 1:0
[DEBUG] [RFNOC::MGMT] * 1:1
[DEBUG] [RFNOC::MGMT] * 1:2
[DEBUG] [RFNOC::MGMT] * 1:3
[DEBUG] [RFNOC::MGMT] * 1:4
[DEBUG] [RFNOC::GRAPH] Connecting the Host to Endpoint 1:0 through Adapter 0 (0
= no preference)...
[DEBUG] [RFNOC::MGMT] Bound stream endpoint with Addr=(1,0) to EPID=2
[DEBUG] [RFNOC] Started thread uhd_ctrl_ep0001 to process messages control
messages on EPID 1
[DEBUG] [RFNOC::MGMT] Established a route from EPID=1 (SW) to EPID=2
[DEBUG] [RFNOC] Created ctrlport endpoint for port 0 on EPID 1
[DEBUG] [RFNOC::GRAPH] Connection to Endpoint 1:0 completed through Device 2.
Using EPIDs 1 -> 2.
[WARNING] [RFNOC::GRAPH] One or more blocks timed out during flush!
[DEBUG] [RFNOC] Created ctrlport endpoint for port 2 on EPID 1
[DEBUG] [0/DUC#0] Checking compat number for FPGA component `0/DUC#0':
Expecting 0.1, actual: 0.1.
[DEBUG] [0/DUC#0] Loading DUC with 3 halfbands and max CIC interpolation 255
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/DUC#0 (NOC ID=d0c00000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 3 on EPID 1
[DEBUG] [0/DDC#0] Checking compat number for FPGA component `0/DDC#0':
Expecting 0.1, actual: 0.1.
[DEBUG] [0/DDC#0] Loading DDC with 3 halfbands and max CIC decimation 255
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/DDC#0 (NOC ID=ddc00000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 4 on EPID 1
[DEBUG] [0/Radio#0] Checking compat number for FPGA component `0/Radio#0':
Expecting 0.0, actual: 0.0.
[DEBUG] [0/Radio#0] ADC capture delay self-cal done (Tap=12, Window=25,
TapDelay=78.125ps, Iter=1)
[DEBUG] [0/Radio#0] Actual sample rate: 200 Msps.
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/Radio#0 (NOC ID=12ad1000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 5 on EPID 1
[DEBUG] [0/DUC#1] Checking compat number for FPGA component `0/DUC#1':
Expecting 0.1, actual: 0.1.
[DEBUG] [0/DUC#1] Loading DUC with 3 halfbands and max CIC interpolation 255
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/DUC#1 (NOC ID=d0c00000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 6 on EPID 1
[DEBUG] [0/DDC#1] Checking compat number for FPGA component `0/DDC#1':
Expecting 0.1, actual: 0.1.
[DEBUG] [0/DDC#1] Loading DDC with 3 halfbands and max CIC decimation 255
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/DDC#1 (NOC ID=ddc00000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 7 on EPID 1
[DEBUG] [0/Radio#1] Checking compat number for FPGA component `0/Radio#1':
Expecting 0.0, actual: 0.0.
[DEBUG] [0/Radio#1] ADC capture delay self-cal done (Tap=18, Window=22,
TapDelay=78.125ps, Iter=1)
[DEBUG] [0/Radio#1] Actual sample rate: 200 Msps.
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/Radio#1 (NOC ID=12ad1000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 8 on EPID 1
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/FFT#0 (NOC ID=ff700000)
[DEBUG] [0/DDC#1] Not setting frequency until sampling rate is set.
[DEBUG] [0/DDC#1] Not setting frequency until sampling rate is set.
[DEBUG] [0/DUC#1] Not setting frequency until sampling rate is set.
[DEBUG] [0/DDC#0] Not setting frequency until sampling rate is set.
[DEBUG] [0/DDC#0] Not setting frequency until sampling rate is set.
[DEBUG] [0/DUC#0] Not setting frequency until sampling rate is set.
[DEBUG] [0/Radio#0] Running ADC self-cal...
[DEBUG] [0/Radio#1] Running ADC self-cal...
Using radio 0, channel 0
Looking for source block 0/Radio#0, port 0
Setting RX Rate: 20.000000 Msps...
DDC block found
Setting decimation value to 10
Actual decimation value is 10
Actual RX Rate: 20.000000 Msps...
Setting RX Freq: 0.000000 MHz...
Actual RX Freq: 10.000000 MHz...
Setting samples per packet to: 256
Actual samples per packet = 256
Using streamer args:
[DEBUG] [CONVERT] get_converter: For converter ID: conversion ID
Input format: sc16_chdr
Num inputs: 1
Output format: sc16
Num outputs: 1
Using prio: 0
[DEBUG] [RFNOC::GRAPH] Initializing data stream from Endpoint 1:0 to Endpoint
1:4...
[DEBUG] [RFNOC::MGMT] Bound stream endpoint with Addr=(1,4) to EPID=3
[DEBUG] [RFNOC::MGMT] Established a route from EPID=1 (SW) to EPID=3
[DEBUG] [RFNOC::MGMT] Established a route from EPID=1 (SW) to EPID=2
[DEBUG] [RFNOC::MGMT] The two routes above now enable a route from EPID=2 to
EPID=3
[DEBUG] [RFNOC::GRAPH] Connection from Endpoint 1:0 to Endpoint 1:4 completed
through Device 2. Using EPIDs 2 -> 3.
[DEBUG] [RFNOC::MGMT] Established a route from EPID=1 (SW) to EPID=3
[DEBUG] [RFNOC::MGMT] Established a route from EPID=1 (SW) to EPID=2
[DEBUG] [RFNOC::MGMT] The two routes above now enable a route from EPID=2 to
EPID=3
[DEBUG] [RFNOC::MGMT] Setup a stream from EPID=2 to EPID=3
[DEBUG] [RFNOC::MGMT] Established a route from EPID=1 (SW) to EPID=3
[DEBUG] [RFNOC::MGMT] Established a route from EPID=1 (SW) to EPID=2
[DEBUG] [RFNOC::MGMT] The two routes above now enable a route from EPID=2 to
EPID=3
[DEBUG] [RFNOC::MGMT] Setup a stream from EPID=2 to EPID=3
[DEBUG] [RFNOC::GRAPH] Data stream between EPID 2 and EPID 3 established where
downstream buffer can hold 262143 bytes and 16777215 packets
[DEBUG] [RFNOC::MGMT] Established a route from EPID=4 (SW) to EPID=3
[DEBUG] [RFNOC::MGMT] Initiated RX stream setup for EPID=3
[DEBUG] [RFNOC::MGMT] Finished RX stream setup for EPID=3
Press Ctrl + C to stop streaming...
Issuing stream cmd
Issuing stop stream cmd
Done!
[DEBUG] [0/FFT#0] deinit() called, but not implemented.
[DEBUG] [0/FFT#0] Invalidating register interface
[DEBUG] [0/Radio#1] Invalidating register interface
[DEBUG] [0/DDC#1] deinit() called, but not implemented.
[DEBUG] [0/DDC#1] Invalidating register interface
[DEBUG] [0/DUC#1] deinit() called, but not implemented.
[DEBUG] [0/DUC#1] Invalidating register interface
[DEBUG] [0/Radio#0] Invalidating register interface
[DEBUG] [0/DDC#0] deinit() called, but not implemented.
[DEBUG] [0/DDC#0] Invalidating register interface
[DEBUG] [0/DUC#0] deinit() called, but not implemented.
[DEBUG] [0/DUC#0] Invalidating register interface
$ ./test --rate 20e6 --block-id 0/Block#0 --spp 256 --progress
Creating the RFNoC graph with args: ...
[INFO] [UHD] linux; GNU C++ version 10.2.1 20201224; Boost_107400; UHD_4.0.0.0-4
[DEBUG] [MPMD] Discovering MPM devices on port 49600
[DEBUG] [MPMD] Discovering MPM devices on port 49600
[DEBUG] [MPMD] Discovering MPM devices on port 49600
[INFO] [X300] X300 initialization sequence...
[DEBUG] [X300] Motherboard 0 has remote device ID: 1
[DEBUG] [X300] Setting up basic communication...
[DEBUG] [X300] Using FPGA version: 38.0 git hash: 1a34ba8-dirty
[DEBUG] [X300] Loading values from EEPROM...
[DEBUG] [X300] Determining maximum frame size...
[INFO] [X300] Maximum frame size: 8000 bytes.
[DEBUG] [X300] Setting up RF frontend clocking...
[DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=8, Requested=0.000000,
Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns
[DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=4, Requested=0.000000,
Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns
[DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=5, Requested=0.000000,
Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns
[DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=0, Requested=0.000000,
Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns
[DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=2, Requested=0.000000,
Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns
[INFO] [X300] Radio 1x clock: 200 MHz
[DEBUG] [X300] Motherboard 0 has local device IDs:
[DEBUG] [X300] * 2
[DEBUG] [RFNOC::MGMT] Starting topology discovery from device:2/sep:1
[DEBUG] [RFNOC::MGMT] Discovered node device:1/xport:0
[DEBUG] [RFNOC::MGMT] Initialized node device:1/xport:0
[DEBUG] [RFNOC::MGMT] Discovered node device:1/xbar:0
[DEBUG] [RFNOC::MGMT] Initialized node device:1/xbar:0
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:0
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:0
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:1
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:1
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:2
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:2
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:3
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:3
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:4
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:4
[DEBUG] [RFNOC::MGMT] The following endpoints are reachable from device:2/sep:1
[DEBUG] [RFNOC::MGMT] * 1:0
[DEBUG] [RFNOC::MGMT] * 1:1
[DEBUG] [RFNOC::MGMT] * 1:2
[DEBUG] [RFNOC::MGMT] * 1:3
[DEBUG] [RFNOC::MGMT] * 1:4
[DEBUG] [RFNOC::GRAPH] Connecting the Host to Endpoint 1:0 through Adapter 0 (0
= no preference)...
[DEBUG] [RFNOC::MGMT] Bound stream endpoint with Addr=(1,0) to EPID=2
[DEBUG] [RFNOC] Started thread uhd_ctrl_ep0001 to process messages control
messages on EPID 1
[DEBUG] [RFNOC::MGMT] Established a route from EPID=1 (SW) to EPID=2
[DEBUG] [RFNOC] Created ctrlport endpoint for port 0 on EPID 1
[DEBUG] [RFNOC::GRAPH] Connection to Endpoint 1:0 completed through Device 2.
Using EPIDs 1 -> 2.
[DEBUG] [RFNOC] Created ctrlport endpoint for port 2 on EPID 1
[DEBUG] [0/DUC#0] Checking compat number for FPGA component `0/DUC#0':
Expecting 0.1, actual: 0.1.
[DEBUG] [0/DUC#0] Loading DUC with 3 halfbands and max CIC interpolation 255
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/DUC#0 (NOC ID=d0c00000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 3 on EPID 1
[DEBUG] [0/DDC#0] Checking compat number for FPGA component `0/DDC#0':
Expecting 0.1, actual: 0.1.
[DEBUG] [0/DDC#0] Loading DDC with 3 halfbands and max CIC decimation 255
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/DDC#0 (NOC ID=ddc00000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 4 on EPID 1
[DEBUG] [0/Radio#0] Checking compat number for FPGA component `0/Radio#0':
Expecting 0.0, actual: 0.0.
[DEBUG] [0/Radio#0] ADC capture delay self-cal done (Tap=12, Window=25,
TapDelay=78.125ps, Iter=1)
[DEBUG] [0/Radio#0] Actual sample rate: 200 Msps.
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/Radio#0 (NOC ID=12ad1000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 5 on EPID 1
[DEBUG] [0/DUC#1] Checking compat number for FPGA component `0/DUC#1':
Expecting 0.1, actual: 0.1.
[DEBUG] [0/DUC#1] Loading DUC with 3 halfbands and max CIC interpolation 255
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/DUC#1 (NOC ID=d0c00000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 6 on EPID 1
[DEBUG] [0/DDC#1] Checking compat number for FPGA component `0/DDC#1':
Expecting 0.1, actual: 0.1.
[DEBUG] [0/DDC#1] Loading DDC with 3 halfbands and max CIC decimation 255
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/DDC#1 (NOC ID=ddc00000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 7 on EPID 1
[DEBUG] [0/Radio#1] Checking compat number for FPGA component `0/Radio#1':
Expecting 0.0, actual: 0.0.
[DEBUG] [0/Radio#1] ADC capture delay self-cal done (Tap=18, Window=22,
TapDelay=78.125ps, Iter=1)
[DEBUG] [0/Radio#1] Actual sample rate: 200 Msps.
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/Radio#1 (NOC ID=12ad1000)
[WARNING] [RFNOC::BLOCK_FACTORY] Could not find block with Noc-ID 0xb16, 0xffff
[DEBUG] [RFNOC] Created ctrlport endpoint for port 8 on EPID 1
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/Block#0 (NOC ID=00000b16)
[DEBUG] [0/DDC#1] Not setting frequency until sampling rate is set.
[DEBUG] [0/DDC#1] Not setting frequency until sampling rate is set.
[DEBUG] [0/DUC#1] Not setting frequency until sampling rate is set.
[DEBUG] [0/DDC#0] Not setting frequency until sampling rate is set.
[DEBUG] [0/DDC#0] Not setting frequency until sampling rate is set.
[DEBUG] [0/DUC#0] Not setting frequency until sampling rate is set.
[DEBUG] [0/Radio#0] Running ADC self-cal...
[DEBUG] [0/Radio#1] Running ADC self-cal...
Using radio 0, channel 0
Looking for source block 0/Radio#0, port 0
Setting RX Rate: 20.000000 Msps...
DDC block found
Setting decimation value to 10
Actual decimation value is 10
Actual RX Rate: 20.000000 Msps...
Setting RX Freq: 0.000000 MHz...
Actual RX Freq: 10.000000 MHz...
Setting samples per packet to: 256
Actual samples per packet = 256
Using streamer args:
[DEBUG] [CONVERT] get_converter: For converter ID: conversion ID
Input format: sc16_chdr
Num inputs: 1
Output format: sc16
Num outputs: 1
Using prio: 0
[DEBUG] [RFNOC::GRAPH] Initializing data stream from Endpoint 1:0 to Endpoint
1:4...
[DEBUG] [RFNOC::MGMT] Bound stream endpoint with Addr=(1,4) to EPID=3
[DEBUG] [RFNOC::MGMT] Established a route from EPID=1 (SW) to EPID=3
[DEBUG] [RFNOC::MGMT] Established a route from EPID=1 (SW) to EPID=2
[DEBUG] [RFNOC::MGMT] The two routes above now enable a route from EPID=2 to
EPID=3
[DEBUG] [RFNOC::GRAPH] Connection from Endpoint 1:0 to Endpoint 1:4 completed
through Device 2. Using EPIDs 2 -> 3.
[DEBUG] [RFNOC::MGMT] Established a route from EPID=1 (SW) to EPID=3
[DEBUG] [RFNOC::MGMT] Established a route from EPID=1 (SW) to EPID=2
[DEBUG] [RFNOC::MGMT] The two routes above now enable a route from EPID=2 to
EPID=3
[DEBUG] [RFNOC::MGMT] Setup a stream from EPID=2 to EPID=3
[DEBUG] [RFNOC::MGMT] Established a route from EPID=1 (SW) to EPID=3
[DEBUG] [RFNOC::MGMT] Established a route from EPID=1 (SW) to EPID=2
[DEBUG] [RFNOC::MGMT] The two routes above now enable a route from EPID=2 to
EPID=3
[DEBUG] [RFNOC::MGMT] Setup a stream from EPID=2 to EPID=3
[DEBUG] [RFNOC::GRAPH] Data stream between EPID 2 and EPID 3 established where
downstream buffer can hold 262143 bytes and 16777215 packets
[DEBUG] [RFNOC::MGMT] Established a route from EPID=4 (SW) to EPID=3
[DEBUG] [RFNOC::MGMT] Initiated RX stream setup for EPID=3
[DEBUG] [RFNOC::MGMT] Finished RX stream setup for EPID=3
Press Ctrl + C to stop streaming...
Issuing stream cmd
Timeout while streaming
Issuing stop stream cmd
Done!
[DEBUG] [0/Block#0] deinit() called, but not implemented.
[DEBUG] [0/Block#0] Invalidating register interface
[DEBUG] [0/Radio#1] Invalidating register interface
[DEBUG] [0/DDC#1] deinit() called, but not implemented.
[DEBUG] [0/DDC#1] Invalidating register interface
[DEBUG] [0/DUC#1] deinit() called, but not implemented.
[DEBUG] [0/DUC#1] Invalidating register interface
[DEBUG] [0/Radio#0] Invalidating register interface
[DEBUG] [0/DDC#0] deinit() called, but not implemented.
[DEBUG] [0/DDC#0] Invalidating register interface
[DEBUG] [0/DUC#0] deinit() called, but not implemented.
[DEBUG] [0/DUC#0] Invalidating register interface
$ ./test --rate 20e6 --spp 256 --progress
Creating the RFNoC graph with args: ...
[INFO] [UHD] linux; GNU C++ version 10.2.1 20201224; Boost_107400; UHD_4.0.0.0-4
[DEBUG] [MPMD] Discovering MPM devices on port 49600
[DEBUG] [MPMD] Discovering MPM devices on port 49600
[DEBUG] [MPMD] Discovering MPM devices on port 49600
[INFO] [X300] X300 initialization sequence...
[DEBUG] [X300] Motherboard 0 has remote device ID: 1
[DEBUG] [X300] Setting up basic communication...
[DEBUG] [X300] Using FPGA version: 38.0 git hash: 1a34ba8-dirty
[DEBUG] [X300] Loading values from EEPROM...
[DEBUG] [X300] Determining maximum frame size...
[INFO] [X300] Maximum frame size: 8000 bytes.
[DEBUG] [X300] Setting up RF frontend clocking...
[DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=8, Requested=0.000000,
Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns
[DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=4, Requested=0.000000,
Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns
[DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=5, Requested=0.000000,
Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns
[DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=0, Requested=0.000000,
Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns
[DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=2, Requested=0.000000,
Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns
[INFO] [X300] Radio 1x clock: 200 MHz
[DEBUG] [X300] Motherboard 0 has local device IDs:
[DEBUG] [X300] * 2
[DEBUG] [RFNOC::MGMT] Starting topology discovery from device:2/sep:1
[DEBUG] [RFNOC::MGMT] Discovered node device:1/xport:0
[DEBUG] [RFNOC::MGMT] Initialized node device:1/xport:0
[DEBUG] [RFNOC::MGMT] Discovered node device:1/xbar:0
[DEBUG] [RFNOC::MGMT] Initialized node device:1/xbar:0
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:0
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:0
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:1
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:1
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:2
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:2
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:3
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:3
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:4
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:4
[DEBUG] [RFNOC::MGMT] The following endpoints are reachable from device:2/sep:1
[DEBUG] [RFNOC::MGMT] * 1:0
[DEBUG] [RFNOC::MGMT] * 1:1
[DEBUG] [RFNOC::MGMT] * 1:2
[DEBUG] [RFNOC::MGMT] * 1:3
[DEBUG] [RFNOC::MGMT] * 1:4
[DEBUG] [RFNOC::GRAPH] Connecting the Host to Endpoint 1:0 through Adapter 0 (0
= no preference)...
[DEBUG] [RFNOC::MGMT] Bound stream endpoint with Addr=(1,0) to EPID=2
[DEBUG] [RFNOC] Started thread uhd_ctrl_ep0001 to process messages control
messages on EPID 1
[DEBUG] [RFNOC::MGMT] Established a route from EPID=1 (SW) to EPID=2
[DEBUG] [RFNOC] Created ctrlport endpoint for port 0 on EPID 1
[DEBUG] [RFNOC::GRAPH] Connection to Endpoint 1:0 completed through Device 2.
Using EPIDs 1 -> 2.
[WARNING] [RFNOC::GRAPH] One or more blocks timed out during flush!
[DEBUG] [RFNOC] Created ctrlport endpoint for port 2 on EPID 1
[DEBUG] [0/DUC#0] Checking compat number for FPGA component `0/DUC#0':
Expecting 0.1, actual: 0.1.
[DEBUG] [0/DUC#0] Loading DUC with 3 halfbands and max CIC interpolation 255
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/DUC#0 (NOC ID=d0c00000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 3 on EPID 1
[DEBUG] [0/DDC#0] Checking compat number for FPGA component `0/DDC#0':
Expecting 0.1, actual: 0.1.
[DEBUG] [0/DDC#0] Loading DDC with 3 halfbands and max CIC decimation 255
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/DDC#0 (NOC ID=ddc00000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 4 on EPID 1
[DEBUG] [0/Radio#0] Checking compat number for FPGA component `0/Radio#0':
Expecting 0.0, actual: 0.0.
[DEBUG] [0/Radio#0] ADC capture delay self-cal done (Tap=12, Window=25,
TapDelay=78.125ps, Iter=1)
[DEBUG] [0/Radio#0] Actual sample rate: 200 Msps.
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/Radio#0 (NOC ID=12ad1000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 5 on EPID 1
[DEBUG] [0/DUC#1] Checking compat number for FPGA component `0/DUC#1':
Expecting 0.1, actual: 0.1.
[DEBUG] [0/DUC#1] Loading DUC with 3 halfbands and max CIC interpolation 255
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/DUC#1 (NOC ID=d0c00000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 6 on EPID 1
[DEBUG] [0/DDC#1] Checking compat number for FPGA component `0/DDC#1':
Expecting 0.1, actual: 0.1.
[DEBUG] [0/DDC#1] Loading DDC with 3 halfbands and max CIC decimation 255
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/DDC#1 (NOC ID=ddc00000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 7 on EPID 1
[DEBUG] [0/Radio#1] Checking compat number for FPGA component `0/Radio#1':
Expecting 0.0, actual: 0.0.
[DEBUG] [0/Radio#1] ADC capture delay self-cal done (Tap=18, Window=22,
TapDelay=78.125ps, Iter=1)
[DEBUG] [0/Radio#1] Actual sample rate: 200 Msps.
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/Radio#1 (NOC ID=12ad1000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 8 on EPID 1
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/FFT#0 (NOC ID=ff700000)
[DEBUG] [0/DDC#1] Not setting frequency until sampling rate is set.
[DEBUG] [0/DDC#1] Not setting frequency until sampling rate is set.
[DEBUG] [0/DUC#1] Not setting frequency until sampling rate is set.
[DEBUG] [0/DDC#0] Not setting frequency until sampling rate is set.
[DEBUG] [0/DDC#0] Not setting frequency until sampling rate is set.
[DEBUG] [0/DUC#0] Not setting frequency until sampling rate is set.
[DEBUG] [0/Radio#0] Running ADC self-cal...
[DEBUG] [0/Radio#1] Running ADC self-cal...
Using radio 0, channel 0
Looking for source block 0/Radio#0, port 0
Setting RX Rate: 20.000000 Msps...
DDC block found
Setting decimation value to 10
Actual decimation value is 10
Actual RX Rate: 20.000000 Msps...
Setting RX Freq: 0.000000 MHz...
Actual RX Freq: 10.000000 MHz...
Setting samples per packet to: 256
Actual samples per packet = 256
Using streamer args:
[DEBUG] [CONVERT] get_converter: For converter ID: conversion ID
Input format: sc16_chdr
Num inputs: 1
Output format: sc16
Num outputs: 1
Using prio: 0
[DEBUG] [RFNOC::MGMT] Established a route from EPID=3 (SW) to EPID=2
[DEBUG] [RFNOC::MGMT] Initiated RX stream setup for EPID=2
[DEBUG] [RFNOC::MGMT] Finished RX stream setup for EPID=2
Press Ctrl + C to stop streaming...
Issuing stream cmd
20.0096 MSps
Issuing stop stream cmd
Done!
[DEBUG] [0/FFT#0] deinit() called, but not implemented.
[DEBUG] [0/FFT#0] Invalidating register interface
[DEBUG] [0/DDC#1] deinit() called, but not implemented.
[DEBUG] [0/DDC#1] Invalidating register interface
[DEBUG] [0/DUC#1] deinit() called, but not implemented.
[DEBUG] [0/DUC#1] Invalidating register interface
[DEBUG] [0/Radio#0] Invalidating register interface
[DEBUG] [0/DDC#0] deinit() called, but not implemented.
[DEBUG] [0/DDC#0] Invalidating register interface
[DEBUG] [0/Radio#1] Invalidating register interface
[DEBUG] [0/DUC#0] deinit() called, but not implemented.
[DEBUG] [0/DUC#0] Invalidating register interface
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