Hi, I'm trying to build an FPGA for the E320. I'm new to Ettus products and RFNoC so this is my attempt.
I'm working with UHD 4.0.0.0 and have been following the tutorial from the 2020 GNU radio conference, RFNoC 4 Workshop. I've used rfmodtool to create a new OOT folder structure. I've then used "rfmodtool add" to add my own IP block. This creates a default .yml file for the for the X210 in the icores folder. Next I've copied the file e320_rfnoc_image_core.yml from the uhd source directory into the icores of folder of my OOT structure, and renamed "demod_e320_rfnoc_image_core.yml" to match the name of new block. I just wanted at this stage to see if I could build the default image, so I haven't changed anything in this .yml file. It seems that I needed to add the IP core to the OTT to get cmake to pick up any build targets. At this stage I just wanted to check that I'd got everything correctly installed and setup on my machine to build the E320 FPGA. I've then created a build folder and ran cmake, sudo make install and then make demod_e320_rfnoc_image_core to build the bitstream. This ran for some time and looked promising. However it eventually failed with the fatal error: "Fatal Python Error : could not acquire lock for <_io.BufferedWriter name ='<stdout>'> at interpreter shutdown, possibly due to daemon threads Python runtime state: finalizing (tstate=0x270bed0)" I did notice scrolling back through the terminal log a number of critical warnings connected with the SPI. "SPI frequency 166.666672 (MHz) should be greater than CPU_1x frequency 166.666672 (MHz)". I don't expect that this is connected with the issue I've seen, and may well be normal. Any help on getting an E320 build going would be greatly appreciated, Mark ________________________________ This email and any files transmitted with it are confidential and intended solely for the use of the individual or entity to whom they are addressed. If you have received this email in error please notify the system manager.
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