On Tue, Jul 14, 2020 at 3:30 PM Richard J. Muri via USRP-users < usrp-users@lists.ettus.com> wrote:
> Hello, > > > > I’m working on a project using x310s where different stakeholders desire > different sampling rates, some of which are not natively support by the > x310. One stakeholder wants to put a fractional resampling filter at the > ingress and egress of the FPGA inside the USRP. > > > > For instance, I may be running the USRP at 50 MHz sampling rate. I have an > application that requires a 40 MHz sampling rate. I want to send 1000 > samples (from my application perspective) loopbacked from TX/RX to RX2. > Does it make sense to put a 5/4 upsampler on the transmit chain inside the > FPGA, and then a 4/5 downsampler on the receive? I’m hoping that if I use > the software I have already written as before, the scenario plays out as > follows: > > > > 1. Initialize the USRP to a 50 MHz sampling rate. > > 2. Set md.time_spec using a clock domain agnostic method (e.g. set > it using integer seconds, double fractional seconds). > > 3. Call tx_streamer->send(txbuffer, 1000 samples, md, 0 timeout) in > my TX thread. > > 4. Call rx_streamer->recv(rxbuffer, 1000 samples, md, 0 timeout) in > my RX thread. > > 5. The 1000 sample TX packet hits the upsampler, gets converted to > 1250 samples. > > 6. The USRP works as normal and puts the 1250 samples through the > full TX/RX chain, at the time specified in the metadata timespec (rounded > to whatever nearest tick count can actually be represented by the 20 ns > clock period) > > 7. The 1250 sample receive hits the downsampler, gets converted to > 1000 samples. > > 8. My software gets 1000 samples into rxbuffer > > > > I’m not terribly familiar with the internal workings of the Verilog > firmware. Are there issues I may be missing? Does the custom firmware need > to intercept the CHDR and change the 1000 samples to 1250, or is the 1000 > only used by software for the network communication? > Rational resampling can work with all the tools that Ettus has already provided. I am in the process of putting the finishing touches on a 2/3 and 3/2 resampler for the X310. I will make it publically available very soon. Let me know if you think this will help you. The DUC and DDC do rate changing, so looking at those as examples, you'll notice that really the big thing to do is check out the axi_rate_change block: https://github.com/EttusResearch/fpga/blob/UHD-3.15.LTS/usrp3/lib/rfnoc/noc_block_ddc.v https://github.com/EttusResearch/fpga/blob/UHD-3.15.LTS/usrp3/lib/rfnoc/noc_block_duc.v https://github.com/EttusResearch/fpga/blob/UHD-3.15.LTS/usrp3/lib/rfnoc/axi_rate_change.v For blocks with fixed rates, check out the DEFAULT_N and DEFAULT_M parameters for the Verilog. This eliminates the need to set a register in software, and the logic in the axi_rate_change block is ready to go at reset. Be sure to simulate the block fully beforehand, but that should do it all for you. Brian
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