Hello,
I'm working on a project using x310s where different stakeholders desire different sampling rates, some of which are not natively support by the x310. One stakeholder wants to put a fractional resampling filter at the ingress and egress of the FPGA inside the USRP. For instance, I may be running the USRP at 50 MHz sampling rate. I have an application that requires a 40 MHz sampling rate. I want to send 1000 samples (from my application perspective) loopbacked from TX/RX to RX2. Does it make sense to put a 5/4 upsampler on the transmit chain inside the FPGA, and then a 4/5 downsampler on the receive? I'm hoping that if I use the software I have already written as before, the scenario plays out as follows: 1. Initialize the USRP to a 50 MHz sampling rate. 2. Set md.time_spec using a clock domain agnostic method (e.g. set it using integer seconds, double fractional seconds). 3. Call tx_streamer->send(txbuffer, 1000 samples, md, 0 timeout) in my TX thread. 4. Call rx_streamer->recv(rxbuffer, 1000 samples, md, 0 timeout) in my RX thread. 5. The 1000 sample TX packet hits the upsampler, gets converted to 1250 samples. 6. The USRP works as normal and puts the 1250 samples through the full TX/RX chain, at the time specified in the metadata timespec (rounded to whatever nearest tick count can actually be represented by the 20 ns clock period) 7. The 1250 sample receive hits the downsampler, gets converted to 1000 samples. 8. My software gets 1000 samples into rxbuffer I'm not terribly familiar with the internal workings of the Verilog firmware. Are there issues I may be missing? Does the custom firmware need to intercept the CHDR and change the 1000 samples to 1250, or is the 1000 only used by software for the network communication? Thank you, Richard
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