OK thanks. So you confirm the link between UHD sample rate and AD93xx sample rate ?
David Le ven. 26 juin 2020 à 00:23, Marcus D. Leech via USRP-users < usrp-users@lists.ettus.com> a écrit : > On 06/25/2020 03:04 PM, David Carsenat via USRP-users wrote: > > Hello. > > We are trying to make a simple RX on TX loopback by changing the FPGA > > image. > > We get it by adding a wire between the DDC output and DUC input, but > > we are still limited by the sample rate we specify via UHD. > > We have specified the analog bandwidth at 56 MHz, and the master > > clock rate at 60 MHz, but no change. > > Same behaviour if we add a wire before the DDC and DUC. We suspect > > a link between UHD sample rate and AD9364 sample rate. > > Is there a way to have the full rate(56 MHz) available on the loopback > > despite, for example, 1MHz sample rate specified via UHD ? > > > > We could also put the sample rate of 56 MHz but the underflow and > > overflow cut the RF signal, perhaps there is a way to avoid this > > phenomenon also. > > > > Thanks a lot. > > > > David > > > My suggestion would be to wade even deeper into the FPGA and have it not > send samples to the host or always only send them at 1Msps, or > something. But regardless, there's no "simple button I can push" to > make this happen. > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
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