Hello. We are trying to make a simple RX on TX loopback by changing the FPGA image. We get it by adding a wire between the DDC output and DUC input, but we are still limited by the sample rate we specify via UHD. We have specified the analog bandwidth at 56 MHz, and the master clock rate at 60 MHz, but no change. Same behaviour if we add a wire before the DDC and DUC. We suspect a link between UHD sample rate and AD9364 sample rate. Is there a way to have the full rate(56 MHz) available on the loopback despite, for example, 1MHz sample rate specified via UHD ?
We could also put the sample rate of 56 MHz but the underflow and overflow cut the RF signal, perhaps there is a way to avoid this phenomenon also. Thanks a lot. David
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