On 03/23/2020 11:08 PM, Lukas Haase wrote:
Hi Marcus,
Gesendet: Freitag, 13. März 2020 um 13:29 Uhr
Von: "Marcus D. Leech" <patchvonbr...@gmail.com>
An: "Lukas Haase" <lukasha...@gmx.at>, "Rob Kossler" <rkoss...@nd.edu>
Cc: "USRP-users@lists.ettus.com" <usrp-users@lists.ettus.com>
Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a
timed command
On 03/13/2020 10:52 AM, Lukas Haase wrote:
Hi again Rob,
Yes, I confirm:
1.) Finally I get the commands to execute at the same time (TX and RX
individually and both at the same time)
2.) Yes, the phase is random after each retune, even when I retune back to the
same frequency
3.) (2) is only true if it includes *DSP* retuning. With naalog retuning
(+integer-N retuning) I get phase coherence, as expected.
I actually expected the PLL retuning much more challenging than the DSP
retuning but for some reason it seems to be the opposite...
It depends on whether the phase-accumulator in the DSP is reset to zero,
or whether just the increment register is updated with the
new phase increment. There are good arguments for both approaches.
I just wanted to check in again if you know how this is implemented and how
your thoughts are regarding tuning in both cases. My take:
Case #1: Phase accumulator and increment register is reset.
- This results in transients when re-tuning frequency because the mixer LO
always (re-)starts at zero phase.
- Since this completely defines the state of the DDC/DUC, I imagine phase
coherence must be preserved assuming the resets in TX and RX happen exactly at
the same time (which is still not certain to me)
According to my study of the FPGA code, the register sets are serialized
within the timed-command FIFO, which is an AXI FIFO, which means
that said commands may be spread over several 10s of nanoseconds in
the X310 (based on a 200MHz system clock).
Case #2: Only increment register is updated
- This results in a smooth transition
- I would guess that this is what USRP implements
- Since not the whole state of DUC/DDC is reset I can imagine there is a
potential for phase coherence problems.
- if I update the phase increment register for DUC to fdsp=500e3 and the
phase increment register for DDC to fdsp=-500e3 can there be any way of
breaking phase coherence? I just can't think of a away (because while the
frequency is different, it's exactly the mirror frequency and results in the
same absolut value)
Thanks,
Lukas
Well, updating the increment register only is "smoother", but not
perfectly smooth, really. Because you're bound to abruptly change the
phase.
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