On 03/19/2020 08:16 PM, Lukas Haase via USRP-users wrote:
Hi Rob,
Sorry I really should have ran the python file before uploading. The
issue was that I combined to files into one and forgot to remove the
imported file.
Here is a new one (tested): http://paste.ubuntu.com/p/VsGRmsbZQ5/
Thanks for reporting your results .... very interesting!
Why do you think second mode makes sense to you? (assuming you are
using timed commands to to retune TX+RX at the same time)
In general, it seems to me that things are related to streaming
start/stop. Maybe things are reset when streaming starts/ends but not
when re-tuning?
Maybe this is what Marcus was mentioning: resetting phase accumulator
vs. "increment register is updated with the new phase increment"?
MAYBE stopping/starting resets the phase accumulator to zero and just
timed retuning doesn't reset anything. But still, my question is left
why this would result in a random phase offset between DUC and DDC.
Thanks again!!
Lukas
So, having spent a couple of hours snooping around the X3xx FPGA code,
where Verilog is not one of my native languages, I have come to
a bit of a conclusion about the ways things work. Now, keep in mind,
this is like me reading War and Peace in the original Russian, and as
an English speaker, coming the vague conclusion that "It was about
Russia".
There's a "settings bus" within the FPGA that is implemented with AXI
FIFO modules. If your command (which results, most often in
having to "set" one or more registers via the settings bus) is not a
timed command, it enters the FIFO, and then is "executed" one
clock later. If it has a time associated with it, then it is
withdrawn when that time has been reached in "vita_time". Note that
since this
is a FIFO, commands that are to be executed "at the same time" will
be serialized by the inherent FIFO nature of execution.
So, with two DDC settings and two DUC settings all sitting in the FIFO,
their actual execution times will be 'spread' over (as far as I can tell)
4 clocks cycles of the FIFO, or about 20nsec. Now in the case where
multiple X3xx are involved, the FIFO will look identical across all
the units, and will execute at the same time, but still be
serialized. But if you have two DDC settings across a pair of X3xx, the
settings
will execute at exactly the same time, since they will in effect be
executing in parallel. Put another way, with shared clocks, and a common
"view" of system time, parallel FIFOs will get drained in the same
order and at the same rate.
Someone with a better understanding of the FPGA really should
comment. But this is my (albeit incomplete) understanding of the
settings-bus logic the FPGA.
Now, even having said THIS, since you'd expect the FIFO to be
deterministic. So, you'd not expect there to be large random
phase offsets that differ from run to run, I think.
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