Greetings Nate,
So been working through your instructions you linked and everything appears
to be good on the software end. It is all cross-compiling and running on
the E312. Unfortunately there appears to be a new issue. So when running
the GUI for building an FGPA bit file, per the instructions, I have
included an FFT, Window, and Fosphor, and selected the option to "File with
FIFOS," which causes the build to fail. The GUI reports for the E310_SG3 it
can support 14 blocks. I tested this with the command line version and 14
also fails. The instructions show a command line option of 5 modules
(blocks) which builds fine. If I up it to 6 it immediately fails. I have
attached a copy of the failure output as a .txt file for 6 blocks.
Regards,
Jon
On Fri, Oct 11, 2019 at 2:51 PM Jonathan Lockhart <jlockhar...@gmail.com>
wrote:
> Greetings Nate,
>
> Thanks for getting back to me so quickly. I will be sure to flash the OS
> to release 4 and roll back my dev environment to match the instructions.
>
> Regards,
> Jon Lockhart
>
>
> On Fri, Oct 11, 2019, 1:20 PM Nate Temple <nate.tem...@ettus.com> wrote:
>
>> Hi Jon,
>>
>> If you are following this app note [0], I would recommend starting with
>> the release-4 image. The pre-3.15 MPM based image that has been released is
>> currently a "beta" release. It lacks several of the dependencies required
>> to build out GNU Radio. We are working on a new release and hope to have it
>> posted soon.
>>
>> [0] -
>> https://kb.ettus.com/Software_Development_on_the_E3xx_USRP_-_Building_RFNoC_UHD_/_GNU_Radio_/_gr-ettus_from_Source
>>
>>
>> Regards,
>> Nate Temple
>>
>> On Fri, Oct 11, 2019 at 10:14 AM Jonathan Lockhart <jlockhar...@gmail.com>
>> wrote:
>>
>>> Greetings Ettus Radio List,
>>>
>>> I have recently acquired and began using an Ettus E312 and have been
>>> trying to configure the dev host and the cross compile environment.
>>> Unfortunately I am having issues completing some of these tasks with the
>>> pre-release version of 3.15 image that Ettus mentions you should use in the
>>> manual for the E312. I forward those issues to support but have heard no
>>> reply. Please refer below to the issues I am reporting. The GNURadio cross
>>> compile issue with the SDK and environment is the more crucial one at the
>>> moment. I was wondering if anyone else has been experiencing these issues
>>> and if so how did you proceed to get it resolved. Is there an image, sdk,
>>> GNURadio version that I should be using other than the 3.15 image and
>>> instructions that Ettus currently recommends using until a stable RC is
>>> provided?
>>>
>>> Thanks for your help and feedback.
>>>
>>> Regards,
>>> Jon Lockhart
>>>
>>>
>>> ---------- Forwarded message ---------
>>> From: Jonathan Lockhart <jlockhar...@gmail.com>
>>> Date: Mon, Oct 7, 2019 at 3:16 PM
>>> Subject: Issues Completing Radio Build and Installation
>>> To: <supp...@ettus.com>
>>>
>>>
>>> Greetings Ettus Support,
>>>
>>> I recently acquired an Ettus E312 and I was looking to do some
>>> development on it. Unfortunately I am have been having some issues. The
>>> manual via files.ettus.com and the "Getting Started" both failed to
>>> provide a working environment.
>>>
>>> The farthest I got was downloading the meta section direction for the
>>> E312 to get 3.15.0 image and sdk for the radio, and then following this
>>> guide page for 3.14, correcting the UHD install accordingly to comply with
>>> 3.15. (Guide
>>> https://kb.ettus.com/Software_Development_on_the_E3xx_USRP_-_Building_RFNoC_UHD_/_GNU_Radio_/_gr-ettus_from_Source#Running_RFNoC_Fosphor
>>> )
>>>
>>> When mounting the cross compiled UHD folders via the instructions on the
>>> radio, and using the uhd_usrp_probe command, there is an error checking for
>>> the libusb_init information.
>>>
>>> root@ni-e31x-313179A:~/newinstall# uhd_usrp_probe
>>> [INFO] [UHD] linux; GNU C++ version 7.3.0; Boost_106600;
>>> UHD_3.15.0.HEAD-0-g6563c537
>>> [ERROR] [UHD] Device discovery error: AssertionError:
>>> libusb_init(&_context) == 0
>>> in libusb_session_impl::libusb_session_impl()
>>> at /home/jon/rfnoc/src/uhd/host/lib/transport/libusb1_base.cpp:36
>>>
>>> [ERROR] [UHD] Device discovery error: AssertionError:
>>> libusb_init(&_context) == 0
>>> in libusb_session_impl::libusb_session_impl()
>>> at /home/jon/rfnoc/src/uhd/host/lib/transport/libusb1_base.cpp:36
>>>
>>> [ERROR] [UHD] Device discovery error: AssertionError:
>>> libusb_init(&_context) == 0
>>> in libusb_session_impl::libusb_session_impl()
>>> at /home/jon/rfnoc/src/uhd/host/lib/transport/libusb1_base.cpp:36
>>>
>>> [INFO] [MPMD] Initializing 1 device(s) in parallel with args:
>>> mgmt_addr=127.0.0.1,type=e3xx,product=e310_sg3,serial=313179A,claimed=False
>>> [INFO] [MPM.PeriphManager] Found 1 daughterboard(s).
>>> [INFO] [MPM.PeriphManager] init() called with device args
>>> `product=e310_sg3,mgmt_addr=127.0.0.1'.
>>> [INFO] [0/Radio_0] Initializing block control (NOC ID:
>>> 0x12AD100000003310)
>>> [INFO] [0/DDC_0] Initializing block control (NOC ID: 0xDDC0000000000000)
>>> [INFO] [0/DUC_0] Initializing block control (NOC ID: 0xD0C0000000000002)
>>> [INFO] [0/Radio_0] RX freq = 2.4e+09
>>> [INFO] [0/Radio_0] RX band = 6
>>> [INFO] [0/Radio_0] RX SW1 = 5
>>> [INFO] [0/Radio_0] RX SWC = 0
>>> [INFO] [0/Radio_0] RX SWB = 1
>>> [INFO] [0/Radio_0] RX VCRX_SW = 1
>>> [INFO] [0/Radio_0] RX VCTXRX_SW = 0
>>> [INFO] [0/Radio_0] RX freq = 2.4e+09
>>> [INFO] [0/Radio_0] RX band = 6
>>> [INFO] [0/Radio_0] RX SW1 = 5
>>> [INFO] [0/Radio_0] RX SWC = 0
>>> [INFO] [0/Radio_0] RX SWB = 1
>>> [INFO] [0/Radio_0] RX VCRX_SW = 1
>>> [INFO] [0/Radio_0] RX VCTXRX_SW = 0
>>> [INFO] [0/Radio_0] RX freq = 2.4e+09
>>> [INFO] [0/Radio_0] RX band = 6
>>> [INFO] [0/Radio_0] RX SW1 = 5
>>> [INFO] [0/Radio_0] RX SWC = 0
>>> [INFO] [0/Radio_0] RX SWB = 1
>>> [INFO] [0/Radio_0] RX VCRX_SW = 1
>>> [INFO] [0/Radio_0] RX VCTXRX_SW = 0
>>> [INFO] [0/Radio_0] RX freq = 2.4e+09
>>> [INFO] [0/Radio_0] RX band = 6
>>> [INFO] [0/Radio_0] RX SW1 = 5
>>> [INFO] [0/Radio_0] RX SWC = 0
>>> [INFO] [0/Radio_0] RX SWB = 1
>>> [INFO] [0/Radio_0] RX VCRX_SW = 1
>>> [INFO] [0/Radio_0] RX VCTXRX_SW = 0
>>> [INFO] [0/Radio_0] RX freq = 2.4e+09
>>> [INFO] [0/Radio_0] RX band = 6
>>> [INFO] [0/Radio_0] RX SW1 = 5
>>> [INFO] [0/Radio_0] RX SWC = 0
>>> [INFO] [0/Radio_0] RX SWB = 1
>>> [INFO] [0/Radio_0] RX VCRX_SW = 1
>>> [INFO] [0/Radio_0] RX VCTXRX_SW = 0
>>> [INFO] [0/Radio_0] RX freq = 2.4e+09
>>> [INFO] [0/Radio_0] RX band = 6
>>> [INFO] [0/Radio_0] RX SW1 = 5
>>> [INFO] [0/Radio_0] RX SWC = 0
>>> [INFO] [0/Radio_0] RX SWB = 1
>>> [INFO] [0/Radio_0] RX VCRX_SW = 1
>>> [INFO] [0/Radio_0] RX VCTXRX_SW = 0
>>> [INFO] [0/Radio_0] Performing CODEC loopback test...
>>> [INFO] [0/Radio_0] CODEC loopback test passed
>>> [INFO] [0/Radio_0] Performing CODEC loopback test...
>>> [INFO] [0/Radio_0] CODEC loopback test passed
>>> _____________________________________________________
>>> /
>>> | Device: E300-Series Device
>>> | _____________________________________________________
>>> | /
>>> | | Mboard: ni-e31x-313179A
>>> | | mpm_version: 3.15.0.git-g6563c537
>>> | | pid: 30675
>>> | | product: e310_sg3
>>> | | rev: 7
>>> | | rpc_connection: local
>>> | | serial: 313179A
>>> | | type: e3xx
>>> | | MPM Version: 1.2
>>> | | FPGA Version: 1.0
>>> | | FPGA git hash: f52a643.clean
>>> | | RFNoC capable: Yes
>>> | |
>>> | | Time sources: internal, external, gpsdo
>>> | | Clock sources: internal
>>> | | Sensors: ref_locked, temp_fpga, temp_mb
>>> | | _____________________________________________________
>>> | | /
>>> | | | RX Dboard: A
>>> | | | _____________________________________________________
>>> | | | /
>>> | | | | RX Frontend: 0
>>> | | | | Name: E3xx
>>> | | | | Antennas: RX2, TX/RX
>>> | | | | Sensors: lo_locked, ad9361_temperature, rssi, lo_lock
>>> | | | | Freq range: 70.000 to 6000.000 MHz
>>> | | | | Gain range PGA: 0.0 to 76.0 step 1.0 dB
>>> | | | | Bandwidth range: 20000000.0 to 40000000.0 step 0.0 Hz
>>> | | | | Connection Type: IQ
>>> | | | | Uses LO offset: No
>>> | | | _____________________________________________________
>>> | | | /
>>> | | | | RX Frontend: 1
>>> | | | | Name: E3xx
>>> | | | | Antennas: RX2, TX/RX
>>> | | | | Sensors: lo_locked, ad9361_temperature, rssi, lo_lock
>>> | | | | Freq range: 70.000 to 6000.000 MHz
>>> | | | | Gain range PGA: 0.0 to 76.0 step 1.0 dB
>>> | | | | Bandwidth range: 20000000.0 to 40000000.0 step 0.0 Hz
>>> | | | | Connection Type: IQ
>>> | | | | Uses LO offset: No
>>> | | | _____________________________________________________
>>> | | | /
>>> | | | | RX Codec: A
>>> | | | | Name: AD9361 Dual ADC
>>> | | | | Gain Elements: None
>>> | | _____________________________________________________
>>> | | /
>>> | | | TX Dboard: A
>>> | | | _____________________________________________________
>>> | | | /
>>> | | | | TX Frontend: 0
>>> | | | | Name: E3xx
>>> | | | | Antennas: TX/RX
>>> | | | | Sensors: lo_locked, ad9361_temperature
>>> | | | | Freq range: 47.000 to 6000.000 MHz
>>> | | | | Gain range PGA: 0.0 to 89.8 step 0.2 dB
>>> | | | | Bandwidth range: 20000000.0 to 40000000.0 step 0.0 Hz
>>> | | | | Connection Type: IQ
>>> | | | | Uses LO offset: No
>>> | | | _____________________________________________________
>>> | | | /
>>> | | | | TX Frontend: 1
>>> | | | | Name: E3xx
>>> | | | | Antennas: TX/RX
>>> | | | | Sensors: lo_locked, ad9361_temperature
>>> | | | | Freq range: 47.000 to 6000.000 MHz
>>> | | | | Gain range PGA: 0.0 to 89.8 step 0.2 dB
>>> | | | | Bandwidth range: 20000000.0 to 40000000.0 step 0.0 Hz
>>> | | | | Connection Type: IQ
>>> | | | | Uses LO offset: No
>>> | | | _____________________________________________________
>>> | | | /
>>> | | | | TX Codec: A
>>> | | | | Name: AD9361 Dual DAC
>>> | | | | Gain Elements: None
>>> | | _____________________________________________________
>>> | | /
>>> | | | RFNoC blocks on this device:
>>> | | |
>>> | | | * Radio_0
>>> | | | * DDC_0
>>> | | | * DUC_0
>>>
>>> It does appear however that the command runs properly even without the
>>> USB files being available.
>>>
>>> As for GNU radio, well that won't cross compile. The base installation
>>> works with no issues, but when I go to cross compile in the SDK environment
>>> for 3.15, I get the following issue:
>>>
>>> ~/rfnoc/src/gnuradio/build-arm$ cmake -Wno-dev
>>> -DCMAKE_TOOLCHAIN_FILE=~/rfnoc/src/gnuradio/cmake/Toolchains/oe-sdk_cross.cmake
>>> -DENABLE_GR_WXGUI=OFF -DENABLE_GR_VOCODER=OFF -DENABLE_GR_DTV=OFF
>>> -DENABLE_GR_ATSC=OFF -DENABLE_DOXYGEN=OFF -DCMAKE_INSTALL_PREFIX=/usr ../
>>> -- Build type not specified: defaulting to release.
>>> -- Build type set to Release.
>>> -- Extracting version information from git describe...
>>> -- Compiler Version: arm-oe-linux-gnueabi-gcc (GCC) 7.3.0
>>> Copyright (C) 2017 Free Software Foundation, Inc.
>>> This is free software; see the source for copying conditions. There is
>>> NO
>>> warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR
>>> PURPOSE.
>>> -- Compiler Flags:
>>> /home/jon/rfnoc/oe/sysroots/x86_64-oesdk-linux/usr/bin/arm-oe-linux-gnueabi/arm-oe-linux-gnueabi-gcc:::-O3
>>> -DNDEBUG -O2 -pipe -g -feliminate-unused-debug-types -std=gnu99
>>> -fvisibility=hidden -Wsign-compare -Wall -Wno-uninitialized
>>> /home/jon/rfnoc/oe/sysroots/x86_64-oesdk-linux/usr/bin/arm-oe-linux-gnueabi/arm-oe-linux-gnueabi-g++:::-O3
>>> -DNDEBUG -O2 -pipe -g -feliminate-unused-debug-types -fvisibility=hidden
>>> -Wsign-compare -Wall -Wno-uninitialized
>>> -- ADDING PERF COUNTERS
>>> -- Building Static Libraries: OFF
>>> -- Boost version: 1.66.0
>>> -- Found the following Boost libraries:
>>> -- date_time
>>> -- program_options
>>> -- filesystem
>>> -- system
>>> -- regex
>>> -- thread
>>> -- chrono
>>> -- atomic
>>> --
>>> -- Checking for module SWIG
>>> -- Found SWIG version 3.0.12.
>>> --
>>> -- The build system will automatically enable all components.
>>> -- Use -DENABLE_DEFAULT=OFF to disable components by default.
>>> --
>>> -- Configuring python-support support...
>>> -- Dependency PYTHONLIBS_FOUND = TRUE
>>> -- Dependency SWIG_FOUND = TRUE
>>> -- Dependency SWIG_VERSION_CHECK = TRUE
>>> -- Enabling python-support support.
>>> -- Override with -DENABLE_PYTHON=ON/OFF
>>> -- Checking for module 'cppunit'
>>> -- No package 'cppunit' found
>>> -- Could NOT find CPPUNIT (missing: CPPUNIT_INCLUDE_DIRS)
>>> --
>>> -- Configuring testing-support support...
>>> -- Dependency CPPUNIT_FOUND = FALSE
>>> CMake Error at cmake/Modules/GrComponent.cmake:75 (message):
>>> user force-enabled testing-support but configuration checked failed
>>> Call Stack (most recent call first):
>>> CMakeLists.txt:373 (GR_REGISTER_COMPONENT)
>>>
>>>
>>> -- Configuring incomplete, errors occurred!
>>> See also
>>> "/home/jon/rfnoc/src/gnuradio/build-arm/CMakeFiles/CMakeOutput.log".
>>> See also
>>> "/home/jon/rfnoc/src/gnuradio/build-arm/CMakeFiles/CMakeError.log".
>>>
>>> I have attached the Output and Error logs as well.
>>>
>>> In comparing the sysroot/ folders under the rfnoc/oe repository, there
>>> is a lot of files missing from the 3.15 build that are in the 3.14 build.
>>> So it appears to be that the SDK is not correct.
>>>
>>> Any assistance in getting these issues resolved would be most helpful.
>>>
>>> Regards,
>>> Jon Lockhart
>>>
>>
Setting up a 64-bit FPGA build environment for the USRP-E3x0...
- Vivado: Found (/opt/Xilinx/Vivado/2017.4/bin)
Environment successfully initialized.
make -f Makefile.e300.inc bin NAME=E310_RFNOC_sg3 ARCH=zynq
PART_ID=xc7z020/clg484/-3 TOP_MODULE=e300 RFNOC=1 E310=1 EXTRA_DEFS="RFNOC=1
E310=1"
make[1]: Entering directory '/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300'
BUILDER: Checking tools...
* GNU bash, version 4.4.20(1)-release (x86_64-pc-linux-gnu)
* Python 2.7.9
* Vivado v2017.4 (64-bit)
[2K
[0mUsing parser configuration from:
/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/dev_config.json[0m
[1;34m[00:00:00] Executing command: vivado -mode batch -source
/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/build_e300.tcl -log build.log
-journal e300.jou[0m
[00:00:00] Current task: Initialization +++ Current Phase: Starting
[2K
[33mCRITICAL WARNING: [Common 17-741] No write access right to the local Tcl
store at '/home/jon/.Xilinx/Vivado/2017.4/XilinxTclStore'. XilinxTclStore is
reverted to the installation area. If you want to use local Tcl Store, please
change the access right and relaunch Vivado.[0m
[00:00:19] Current task: Initialization +++ Current Phase: Finished
[2K
[1;34m[00:00:19] Executing Tcl: synth_design -top e300 -part xc7z020clg484-3
-verilog_define RFNOC=1 -verilog_define E310=1 -verilog_define
GIT_HASH=32'hfbb85bdf -directive AreaOptimized_high[0m
[32m[00:00:19] Starting Synthesis Command[0m
[00:00:19] Current task: Synthesis +++ Current Phase: Starting
[2K
[33mCRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s)
found for '-group [get_clocks -include_generated_clocks clk_fpga_0]'.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:20][0m
[33mCRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s)
found for '-group [get_clocks -include_generated_clocks clk0]'.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:28][0m
[33mCRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s)
found for '-group [get_clocks -include_generated_clocks clkdv]'.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:28][0m
[00:01:52] Current task: Synthesis +++ Current Phase: Loading Part and Timing
Information
[2K
[00:02:12] Current task: Synthesis +++ Current Phase: RTL Component Statistics
[2K
[00:02:12] Current task: Synthesis +++ Current Phase: RTL Hierarchical
Component Statistics
[2K
[00:02:12] Current task: Synthesis +++ Current Phase: Part Resource Summary
[2K
[00:03:15] Current task: Synthesis +++ Current Phase: Cross Boundary and Area
Optimization
[2K
[00:06:01] Current task: Synthesis +++ Current Phase: Applying XDC Timing
Constraints
[2K
[00:06:05] Current task: Synthesis +++ Current Phase: Timing Optimization
[2K
[00:06:31] Current task: Synthesis +++ Current Phase: Technology Mapping
[2K
[00:07:43] Current task: Synthesis +++ Current Phase: IO Insertion
[2K
[00:07:43] Current task: Synthesis +++ Current Phase: Flattening Before IO
Insertion
[2K
[00:07:48] Current task: Synthesis +++ Current Phase: Final Netlist Cleanup
[2K
[00:08:01] Current task: Synthesis +++ Current Phase: Renaming Generated
Instances
[2K
[00:08:13] Current task: Synthesis +++ Current Phase: Rebuilding User Hierarchy
[2K
[00:08:22] Current task: Synthesis +++ Current Phase: Renaming Generated Ports
[2K
[00:08:26] Current task: Synthesis +++ Current Phase: Handling Custom Attributes
[2K
[00:08:26] Current task: Synthesis +++ Current Phase: Renaming Generated Nets
[2K
[00:08:26] Current task: Synthesis +++ Current Phase: Writing Synthesis Report
[2K
[00:08:30] Current task: Synthesis +++ Current Phase: Finished
[2K
[32m[00:08:30] Translating Synthesized Netlist[0m
[00:08:30] Current task: Translating Synthesized Netlist +++ Current Phase:
Starting[2K
[33mCRITICAL WARNING: [Designutils 20-1281] Could not find module
'mig_7series_0'. The XDC file
/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-3/mig_7series_0/mig_7series_0/user_design/constraints/mig_7series_0.xdc
will not be read for this module.[0m
[33mCRITICAL WARNING: [Designutils 20-1280] Could not find module 'axi_hb31'.
The XDC file
/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_hb31/constraints/fir_compiler_v7_2.xdc
will not be read for any cell of this module.[0m
[33mCRITICAL WARNING: [Designutils 20-1280] Could not find module 'axi_hb47'.
The XDC file
/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_hb47/constraints/fir_compiler_v7_2.xdc
will not be read for any cell of this module.[0m
[33mCRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s)
found for '-group [get_clocks -include_generated_clocks clk0]'.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:28][0m
[33mCRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s)
found for '-group [get_clocks -include_generated_clocks clkdv]'.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:28][0m
[33mCRITICAL WARNING: [Constraints 18-4644] set_clock_groups: All clock groups
specified are empty. Please specify atleast one clock group which is not empty.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:28][0m
[33mCRITICAL WARNING: [Common 17-161] Invalid option value '#' specified for
'objects'.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:53][0m
[33mCRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by
forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing
paths to this pin unless set_min_delay is used to constrain the paths.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58][0m
[33mCRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by
forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing
paths to this pin unless set_min_delay is used to constrain the paths.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58][0m
[33mCRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by
forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing
paths to this pin unless set_min_delay is used to constrain the paths.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58][0m
[00:10:00] Current task: Translating Synthesized Netlist +++ Current Phase:
Starting
[2K
[00:11:51] Current task: Translating Synthesized Netlist +++ Current Phase:
Finished
[2K
[1;34m[00:11:51] Executing Tcl: report_drc -ruledeck methodology_checks -file
/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/build-E310_RFNOC_sg3/methodology.rpt[0m
[32m[00:11:51] Starting DRC Command[0m
[00:11:51] Current task: DRC +++ Current Phase: Starting
[2K
[33mCRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by
forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing
paths to this pin unless set_min_delay is used to constrain the paths.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58][0m
[33mCRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by
forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing
paths to this pin unless set_min_delay is used to constrain the paths.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58][0m
[33mCRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by
forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing
paths to this pin unless set_min_delay is used to constrain the paths.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58][0m
[33mCRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by
forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing
paths to this pin unless set_min_delay is used to constrain the paths.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58][0m
[33mCRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by
forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing
paths to this pin unless set_min_delay is used to constrain the paths.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58][0m
[33mCRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by
forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing
paths to this pin unless set_min_delay is used to constrain the paths.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58][0m
[00:14:23] Current task: DRC +++ Current Phase: Finished
[2K
[1;34m[00:14:23] Executing Tcl: opt_design -directive NoBramPowerOpt[0m
[32m[00:14:23] Starting Logic Optimization Command[0m
[00:14:23] Current task: Logic Optimization +++ Current Phase: Starting
[2K
[00:14:24] Current task: Logic Optimization +++ Current Phase: Finished
[2K
[32m[00:14:24] Starting DRC Task[0m
[00:14:24] Current task: DRC +++ Current Phase: Starting
[2K
[00:14:26] Current task: DRC +++ Current Phase: Finished
[2K
[32m[00:14:26] Starting Logic Optimization Task[0m
[00:14:26] Current task: Logic Optimization +++ Current Phase: Starting
[2K
[33mCRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by
forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing
paths to this pin unless set_min_delay is used to constrain the paths.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58][0m
[33mCRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by
forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing
paths to this pin unless set_min_delay is used to constrain the paths.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58][0m
[33mCRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by
forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing
paths to this pin unless set_min_delay is used to constrain the paths.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58][0m
[00:14:52] Current task: Logic Optimization +++ Current Phase: 1 Retarget
[2K
[00:15:06] Current task: Logic Optimization +++ Current Phase: 2 Constant
propagation
[2K
[00:15:11] Current task: Logic Optimization +++ Current Phase: 3 Sweep
[2K
[00:15:30] Current task: Logic Optimization +++ Current Phase: 4 BUFG
optimization
[2K
[00:15:36] Current task: Logic Optimization +++ Current Phase: 5 Shift Register
Optimization
[2K
[00:15:46] Current task: Logic Optimization +++ Current Phase: Finished
[2K
[32m[00:15:46] Starting Connectivity Check Task[0m
[00:15:46] Current task: Connectivity Check +++ Current Phase: Starting
[2K
[00:15:51] Current task: Connectivity Check +++ Current Phase: Finished
[2K
[1;34m[00:15:51] Executing Tcl: place_design -directive ExtraNetDelay_high[0m
[32m[00:15:51] Starting Placer Command[0m
[00:15:51] Current task: Placer +++ Current Phase: Starting
[2K
[32m[00:16:08] Starting Placer Task[0m
[00:16:08] Current task: Placer +++ Current Phase: Starting
[2K
[00:16:08] Current task: Placer +++ Current Phase: 1 Placer Initialization
[2K
[00:16:08] Current task: Placer +++ Current Phase: 1.1 Placer Initialization
Netlist Sorting
[2K
[33mCRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by
forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing
paths to this pin unless set_min_delay is used to constrain the paths.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58][0m
[33mCRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by
forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing
paths to this pin unless set_min_delay is used to constrain the paths.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58][0m
[33mCRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by
forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing
paths to this pin unless set_min_delay is used to constrain the paths.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58][0m
[00:16:36] Current task: Placer +++ Current Phase: 1.2 IO Placement/ Clock
Placement/ Build Placer Device
[2K
[33mCRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by
forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing
paths to this pin unless set_min_delay is used to constrain the paths.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58][0m
[33mCRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by
forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing
paths to this pin unless set_min_delay is used to constrain the paths.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58][0m
[33mCRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by
forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing
paths to this pin unless set_min_delay is used to constrain the paths.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58][0m
[00:17:12] Current task: Placer +++ Current Phase: 1.3 Build Placer Netlist
Model
[2K
[33mCRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by
forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing
paths to this pin unless set_min_delay is used to constrain the paths.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58][0m
[33mCRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by
forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing
paths to this pin unless set_min_delay is used to constrain the paths.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58][0m
[33mCRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by
forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing
paths to this pin unless set_min_delay is used to constrain the paths.
[/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58][0m
[00:18:05] Current task: Placer +++ Current Phase: 1.4 Constrain Clocks/Macros
[2K
[00:18:06] Current task: Placer +++ Current Phase: 2 Global Placement
[2K
[00:19:25] Current task: Placer +++ Current Phase: 3 Detail Placement
[2K
[00:19:25] Current task: Placer +++ Current Phase: 3.1 Commit Multi Column
Macros[2K
[00:20:00] Current task: Placer +++ Current Phase: 3.1 Commit Multi Column
Macros
[2K
[00:20:15] Current task: Placer +++ Current Phase: 3.3 Area Swap Optimization
[2K
[00:20:16] Current task: Placer +++ Current Phase: 3.4 Pipeline Register
Optimization
[2K
[00:20:16] Current task: Placer +++ Current Phase: 3.5 Small Shape Detail
Placement
[2K
[1;31mERROR: [Place 30-487] The packing of instances into the device could not
be obeyed. There are a total of 13300 slices in the pblock, of which 8802
slices are available, however, the unplaced instances require 9260 slices.
Please analyze your design to determine if the number of LUTs, FFs, and/or
control sets can be reduced.[0m
[1;31mERROR: [Place 30-99] Placer failed with error: 'Detail Placement failed
please check previous errors for details.'[0m
[1;31mERROR: [Common 17-69] Command failed: Placer could not place all
instances[0m
[00:20:49] Current task: Placer +++ Current Phase: Finished
[1;31m[00:20:49] Process terminated. Status: Failure[0m
========================================================
Warnings: 655
Critical Warnings: 32
Errors: 3
Makefile.e300.inc:98: recipe for target 'bin' failed
make[1]: *** [bin] Error 1
make[1]: Leaving directory '/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300'
Makefile:70: recipe for target 'E310_RFNOC_sg3' failed
make: *** [E310_RFNOC_sg3] Error 2
--Using the following blocks to generate image:
* fft
* window
* fosphor
Adding CE instantiation file for 'E310_RFNOC_sg3'
changing temporarily working directory to
/home/jon/rfnoc/src/uhd/fpga-src/usrp3/tools/scripts/../../top/e300
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