Hi Royce, Can you walk me through your use case real quick?
- How many channels? - How wide is each channel? - Are the channels equally spaced? The polyphase channelizer in theseus-cores currently has a static number of "max channels" that get instantiated.... which is not insignificant. We've discussed exposing a build-time parameter that could scale down the max number of channels to save some resources, but 1) that hasn't been implemented yet and 2) I'm not totally confident it would fit in the e310 anyway. But lets think through your scenario and we can discuss where we'd need the channelizer to go for it to work... for example, you probably also need the FPGA-based channel downselection in the channelizer -- the E310 wont be able to return all channels in real time! Or, we could consider other approaches -- the DDC channelizer in theseus-cores might be workable if you have just small number of channels and you need arbitrary spacing/channel widths. EJ On Thu, Aug 8, 2019, 8:52 AM Royce Connerley <royceconner...@yahoo.com> wrote: > EJ: > > I want to pick a few narrowband channels scattered over about 5 MHz. I > would like to be able to use your channelizer in an E310. Do you think it > could fit in the E310’s FPGA? When I run uhd_image_builder with just the > channelizer and a FIFO, I’m seeing the following errors: > > ERROR: [Place 30-640] Place Check : This design requires more RAMB36/FIFO > cells than are available in the target device. This design requires 324 of > such cell types but only 140 compatible sites are available in the target > device. Please analyze your synthesis results and constraints to ensure the > design is mapped to Xilinx primitives as expected. If so, please consider > targeting a larger device. > ERROR: [Place 30-640] Place Check : This design requires more RAMB18 and > RAMB36/FIFO cells than are available in the target device. This design > requires 703 of such cell types but only 280 compatible sites are available > in the target device. Please analyze your synthesis results and constraints > to ensure the design is mapped to Xilinx primitives as expected. If so, > please consider targeting a larger device. > ERROR: [Place 30-640] Place Check : This design requires more RAMB36E1 > cells than are available in the target device. This design requires 324 of > such cell types but only 140 compatible sites are available in the target > device. Please analyze your synthesis results and constraints to ensure the > design is mapped to Xilinx primitives as expected. If so, please consider > targeting a larger device. > > Royce Connerley > > On Jul 24, 2019, at 6:34 PM, EJ Kreinar <ejkrei...@gmail.com> wrote: > > Hi Royce, > > Phil and I have been working on the channelizer in the theseus-cores repo > here: gitlab.com/theseus-cores/theseus-cores > > The master branch has a (potentially) working channelizer, at least > according to my recent tests on the x310, as long as the network interface > supports the desired output rate. > > There's also an fpga solution for channel downselection in a branch that > Phil put together. The ball is in my court to turn the crank and merge to > master with supporting software, but I haven't gotten much of a chance > recently. > > If you're interested in testing we could definitely use some more people > to give it a shot :D Let me know if you need a sample bitstream or if you > can build one yourself. > > EJ > > On Wed, Jul 24, 2019, 4:39 PM Royce Connerley via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> At the 2018 GRCon, EJ Kreinar spoke about improvements to the RFNoC >> polyphase channelizer. Has there been any activity on this? >> >> Royce Connerley >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> > >
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