See interleaved responses below. On Wed, Jul 10, 2019 at 6:42 AM Samuel Berhanu via USRP-users < usrp-users@lists.ettus.com> wrote:
> The N310 design (i have tried both the HG and XG ) specify the following: > UART0 on MIO pin 14:15, > PJTAG on pin 10:13 > UART1 on MIO pin 8:9 > I2C0 on MIO pin 50:51 > > there is also GPIO pins on 46:49. > > All the above pins when looking at the MB schematic have different > assignments. > Namely, > MIO 14:15 -> PS-I2C0-SCL, PS-I2C0-SDA > MIO 10:13 -> PS-UART0-RX, PS-UART0-TX,SYS-PS-I2C-SCL, ...SDA > et.al > > 1) In short, which one is correct? Datasheet or NI design? and whichever > is corect, does that hold true for all the other connections also? > The pinouts in the Vivado TCL file are the correct ones-- https://github.com/EttusResearch/fpga/blob/UHD-3.14/usrp3/top/n3xx/ip/n310_ps_bd/n310_ps_bd.tcl > 2) I only see one of the two I2C controllers enabled in the PS. Where is > SYS-PS-I2C-SCL coming from the schematic? > > It's connected to the STM32 microcontroller (U55). > 3) Where is the microcontroller code for the STM32F072RBT6 code located? I > tried looking under ./firmware but I dont see it? > > The ChromeOS source code for the STM32 MCU is in the usrp-firmware repo in the EttusResearch github. More specifically: https://github.com/EttusResearch/usrp-firmware/tree/sulfur/board/sulfur > 4) Am i correct in assuming for all FPGA images except White Rabbit, the > phase dac that is used for controlling VCXO is set at just about mid-range > and does not get adjusted? In general, a clearer picture of what the values > are being programmed in the LMK and their sequence or an overview of the > clock output values generated would be appreciated. > > I'm not sure-- maybe someone still employed by NI could answer this question. More details on the LMK settings are in the DB FPGA folder: https://github.com/EttusResearch/fpga/blob/UHD-3.14/usrp3/top/n3xx/dboards/mg/db_timing.xdc > Thank you, > > Samuel Berhanu > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
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