Hi Brent, What's the ballpark programming time using uhd_image_loader on the e310?
I currently swap in/out fpga images using the args parameter on the e310 since the fpga size is pretty small. In some cases the application introspects the required fpga resources, and dynamically chooses the correct bitstream at runtime... Just wondering if there's a way I can use a similar workflow with uhd_image_loader on the MPM architecture... EJ On Fri, Jun 28, 2019, 9:07 PM Brent Stapleton via USRP-users < usrp-users@lists.ettus.com> wrote: > The 3.15 pre-release updates the E310 to use MPM (as you know), and brings > it more in line with other MPM devices. You'll have to use the > `uhd_image_loader` to update the FPGA image; device args are not used by > the UHD session to load the FPGA image. The E310 will still load the FPGA > image at the beginning of the session (and load an idle image when there is > no active UHD session), but that image is not determined by the session. > You shouldn't need to touch it manually (we recommend using > uhd_image_loader), but the image is stored on the filesystem at > /lib/firmware/e310_sg1.bin. > > Brent > > On Fri, Jun 28, 2019 at 5:27 PM d.des via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Marcus Leach wrote: >> >What happens if you specify an fpga image that doesn't actually >> >exist? >> >Does it error out? >> >> >> It ignores the bad file, even though the args seem to be making it >> pretty far into the process. I still can't find where uhd loads the >> .bit file. >> >> I'm using the version on the referenced SD image from Ettus's site, not >> bit-baking the latest from meta-ettus. >> >> Here's the result for the pre-compiled uhd that was on the SD image at >> debug log level 0: The results are similar on >> >> root@ni-e31x-309C7C2F:~# uhd_usrp_probe -- >> args="fpga=filethatdoesntexist" >> [INFO] [UHD] linux; GNU C++ version 7.3.0; Boost_106600; >> UHD_3.15.0.git-0-g6563c537 >> [DEBUG] [MPMD] Discovering MPM devices on port 49600 >> [DEBUG] [MPMD] Discovering MPM devices on port 49600 >> [TRACE] [UDP] Creating udp transport for 10.1.1.255 49600 >> [TRACE] [UDP] Creating udp transport for 127.255.255.255 49600 >> [TRACE] [UDP] Creating udp transport for 10.1.1.255 50000 >> [TRACE] [UHD] Device hash: 2130689100 >> [DEBUG] [PREFS] Loaded system config file /etc/uhd/uhd.conf >> [DEBUG] [PREFS] Loaded user config file /home/root/.uhd/uhd.conf >> [DEBUG] [PREFS] Loaded system config file /etc/uhd/uhd.conf >> [DEBUG] [PREFS] Loaded user config file /home/root/.uhd/uhd.conf >> [DEBUG] [PREFS] Loaded system config file /etc/uhd/uhd.conf >> [DEBUG] [PREFS] Loaded user config file /home/root/.uhd/uhd.conf >> [INFO] [MPMD] Initializing 1 device(s) in parallel with args: >> mgmt_addr=127.0.0.1,type=e3xx,product=e310_sg1,serial=309C7C2,claimed=F >> alse,fpga=filethatdoesntexist >> [DEBUG] [MPMD] Claiming mboard 0 >> [DEBUG] [MPMD] Device args: >> `mgmt_addr=127.0.0.1,type=e3xx,product=e310_sg1,serial=309C7C2,claimed= >> False,fpga=filethatdoesntexist'. RPC address: 127.0.0.1 >> [TRACE] [MPMD] Initializing mboard, connecting to RPC server address: >> 127.0.0.1 mboard args: >> mgmt_addr=127.0.0.1,type=e3xx,product=e310_sg1,serial=309C7C2,claimed=F >> alse,fpga=filethatdoesntexist number of crossbars: 1 >> [INFO] [MPM.PeriphManager] Found 1 daughterboard(s). >> [TRACE] [MPMD] MPM reports device info: >> claimed=True,connection=local,description=E300-Series >> Device,eeprom_version=,fpga=,fpga_version=1.0,fpga_version_hash=f52a643 >> .clean,mpm_version=1.2,name=ni-e31x- >> 309C7C2F,pid=30674,product=e310_sg1,rev=4,rpc_connection=local,serial=3 >> 09C7C2,type=e3xx >> [TRACE] [MPMD] MPM reports dboard info for slot 0: >> eeprom_version=n/a,pid=272,rev=3,serial=309991A >> [TRACE] [MPMD] Checking MPM compat number. Expected: 1.2 Actual: 1.2 >> [DEBUG] [MPMD] Initializing mboard 0 >> [DEBUG] [MPMD] Found 3 motherboard sensors. >> [DEBUG] [MPMD] Found 2 updateable motherboard components. >> [TRACE] [MPMD] Enumerating RFNoC blocks for xbar 0. Total blocks: 3 >> Base port: 1 Local address: 2 >> [TRACE] [MPMD] Creating new transport to mboard: 0 SID: 00:00>02:10 >> User-defined xport args: >> mgmt_addr=127.0.0.1,type=e3xx,product=e310_sg1,serial=309C7C2,claimed=F >> alse,fpga=filethatdoesntexist >> [TRACE] [MPMD] make_transport(): Creating new transport of type: CTRL >> [TRACE] [MPMD] make_transport(): request_xport() gave us 1 option(s). >> [TRACE] [MPMD] Making (muxed) stream with num 0 >> [TRACE] [MPMD] xport info: send_sid==00:00>02:10 recv_sid==02:10>00:00 >> endianness==LE recv_buff_size==10880 send_buff_size==10880 >> [DEBUG] [DEVICE3] Port 0x10: Found NoC-Block with ID 12AD100000003310. >> [DEBUG] [RFNOC] Reading XML file >> /usr/share/uhd/rfnoc/blocks/radio_e31x.xml for NOC ID >> 0x12AD100000003310 >> [TRACE] [MPMD] Creating new transport to mboard: 0 SID: 00:00>02:11 >> User-defined xport args: >> mgmt_addr=127.0.0.1,type=e3xx,product=e310_sg1,serial=309C7C2,claimed=F >> alse,fpga=filethatdoesntexist >> [TRACE] [MPMD] make_transport(): Creating new transport of type: CTRL >> [TRACE] [MPMD] make_transport(): request_xport() gave us 1 option(s). >> [TRACE] [MPMD] Making (muxed) stream with num 1 >> [TRACE] [MPMD] xport info: send_sid==00:01>02:11 recv_sid==02:11>00:01 >> endianness==LE recv_buff_size==10880 send_buff_size==10880 >> [TRACE] [RFNOC] [RFNoC Factory] block_ctrl_base::make() >> [DEBUG] [RFNOC] Reading XML file >> /usr/share/uhd/rfnoc/blocks/radio_e31x.xml for NOC ID >> 0x12AD100000003310 >> [TRACE] [RFNOC] [RFNoC Factory] Using controller key 'E31XRadio' and >> block name 'Radio' >> [DEBUG] [RFNOC] Reading XML file >> /usr/share/uhd/rfnoc/blocks/radio_e31x.xml for NOC ID >> 0x12AD100000003310 >> [INFO] [0/Radio_0] Initializing block control (NOC ID: >> 0x12AD100000003310) >> [DEBUG] [0/Radio_0] Checking compat number for FPGA component >> `noc_shell': Expecting 5.1, actual: 5.1. >> [TRACE] [0/Radio_0] Adding port definition at xbar/Radio_0/ports/in/0: >> type = 'sc16' pkt_size = '0' vlen = '0' >> [TRACE] [0/Radio_0] Adding port definition at xbar/Radio_0/ports/in/1: >> type = 'sc16' pkt_size = '0' vlen = '0' >> [TRACE] [0/Radio_0] Adding port definition at xbar/Radio_0/ports/out/0: >> type = 'sc16' pkt_size = '0' vlen = '0' >> [TRACE] [0/Radio_0] Adding port definition at xbar/Radio_0/ports/out/1: >> type = 'sc16' pkt_size = '0' vlen = '0' >> [DEBUG] [0/Radio_0] Register loopback test passed >> [DEBUG] [0/Radio_0] Register loopback test passed >> [TRACE] [RFNOC] radio_ctrl_impl::_update_spp(): Requested spp: 508 >> [TRACE] [RFNOC] radio_ctrl_impl::_update_spp(): Setting spp to: 508 >> [DEBUG] [0/Radio_0] Setting default spp to 2044 >> [TRACE] [RFNOC] radio_ctrl_impl::_update_spp(): Requested spp: 2044 >> [TRACE] [RFNOC] radio_ctrl_impl::_update_spp(): Setting spp to: 2044 >> [TRACE] [MPMD] Creating new transport to mboard: 0 SID: 00:00>02:20 >> User-defined xport args: >> mgmt_addr=127.0.0.1,type=e3xx,product=e310_sg1,serial=309C7C2,claimed=F >> alse,fpga=filethatdoesntexist >> [TRACE] [MPMD] make_transport(): Creating new transport of type: CTRL >> [TRACE] [MPMD] make_transport(): request_xport() gave us 1 option(s). >> [TRACE] [MPMD] Making (muxed) stream with num 2 >> [TRACE] [MPMD] xport info: send_sid==00:02>02:20 recv_sid==02:20>00:02 >> endianness==LE recv_buff_size==10880 send_buff_size==10880 >> [DEBUG] [DEVICE3] Port 0x20: Found NoC-Block with ID DDC0000000000000. >> [DEBUG] [RFNOC] Reading XML file /usr/share/uhd/rfnoc/blocks/ddc.xml >> for NOC ID 0xDDC0000000000000 >> [TRACE] [MPMD] Creating new transport to mboard: 0 SID: 00:00>02:21 >> User-defined xport args: >> mgmt_addr=127.0.0.1,type=e3xx,product=e310_sg1,serial=309C7C2,claimed=F >> alse,fpga=filethatdoesntexist >> [TRACE] [MPMD] make_transport(): Creating new transport of type: CTRL >> [TRACE] [MPMD] make_transport(): request_xport() gave us 1 option(s). >> [TRACE] [MPMD] Making (muxed) stream with num 3 >> [TRACE] [MPMD] xport info: send_sid==00:03>02:21 recv_sid==02:21>00:03 >> endianness==LE recv_buff_size==10880 send_buff_size==10880 >> [TRACE] [RFNOC] [RFNoC Factory] block_ctrl_base::make() >> [DEBUG] [RFNOC] Reading XML file /usr/share/uhd/rfnoc/blocks/ddc.xml >> for NOC ID 0xDDC0000000000000 >> [TRACE] [RFNOC] [RFNoC Factory] Using controller key 'DDC' and block >> name 'DDC' >> [DEBUG] [RFNOC] Reading XML file /usr/share/uhd/rfnoc/blocks/ddc.xml >> for NOC ID 0xDDC0000000000000 >> [INFO] [0/DDC_0] Initializing block control (NOC ID: >> 0xDDC0000000000000) >> [DEBUG] [0/DDC_0] Checking compat number for FPGA component >> `noc_shell': Expecting 5.1, actual: 5.1. >> [INFO] [MPM.PeriphManager] init() called with device args >> `fpga=filethatdoesntexist,mgmt_addr=127.0.0.1,product=e310_sg1'. >> [TRACE] [0/DDC_0] Adding port definition at xbar/DDC_0/ports/in/0: type >> = 'sc16' pkt_size = '0' vlen = '0' >> [TRACE] [0/DDC_0] Adding port definition at xbar/DDC_0/ports/in/1: type >> = 'sc16' pkt_size = '0' vlen = '0' >> [TRACE] [0/DDC_0] Adding port definition at xbar/DDC_0/ports/out/0: >> type = 'sc16' pkt_size = '0' vlen = '0' >> [TRACE] [0/DDC_0] Adding port definition at xbar/DDC_0/ports/out/1: >> type = 'sc16' pkt_size = '0' vlen = '0' >> [TRACE] [RFNOC] [NocScript] Executing and asserting code: >> GE($input_rate, 0.0) >> [TRACE] [RFNOC] [NocScript] Executing and asserting code: >> GE($output_rate, 0.0) >> [TRACE] [RFNOC] [NocScript] Executing and asserting code: >> GE($fullscale, 0.0) >> [TRACE] [RFNOC] [NocScript] Executing and asserting code: >> GE($input_rate, 0.0) >> [TRACE] [RFNOC] [NocScript] Executing and asserting code: >> GE($output_rate, 0.0) >> [TRACE] [RFNOC] [NocScript] Executing and asserting code: >> GE($fullscale, 0.0) >> [DEBUG] [0/DDC_0] Loading DDC with 1 halfbands and max CIC decimation >> 16 >> [DEBUG] [DDC] Checking compat number for FPGA component `DDC': >> Expecting 2.0, actual: 2.0. >> [TRACE] [RFNOC] [NocScript] Executing and asserting code: >> GE($output_rate, 0.0) >> [TRACE] [RFNOC] [NocScript] Executing and asserting code: >> GE($output_rate, 0.0) >> [TRACE] [MPMD] Creating new transport to mboard: 0 SID: 00:00>02:30 >> User-defined xport args: >> mgmt_addr=127.0.0.1,type=e3xx,product=e310_sg1,serial=309C7C2,claimed=F >> alse,fpga=filethatdoesntexist >> >> ---note: args=fpga= points to non-existant files, and there are no .bit >> files anywhere on the sd card >> >> [TRACE] [MPMD] make_transport(): Creating new transport of type: CTRL >> [TRACE] [MPMD] make_transport(): request_xport() gave us 1 option(s). >> [TRACE] [MPMD] Making (muxed) stream with num 4 >> [TRACE] [MPMD] xport info: send_sid==00:04>02:30 recv_sid==02:30>00:04 >> endianness==LE recv_buff_size==10880 send_buff_size==10880 >> [DEBUG] [DEVICE3] Port 0x30: Found NoC-Block with ID D0C0000000000002. >> [DEBUG] [RFNOC] Reading XML file /usr/share/uhd/rfnoc/blocks/duc.xml >> for NOC ID 0xD0C0000000000002 >> [TRACE] [MPMD] Creating new transport to mboard: 0 SID: 00:00>02:31 >> User-defined xport args: >> mgmt_addr=127.0.0.1,type=e3xx,product=e310_sg1,serial=309C7C2,claimed=F >> alse,fpga=filethatdoesntexist >> [TRACE] [MPMD] make_transport(): Creating new transport of type: CTRL >> [TRACE] [MPMD] make_transport(): request_xport() gave us 1 option(s). >> [TRACE] [MPMD] Making (muxed) stream with num 5 >> [TRACE] [MPMD] xport info: send_sid==00:05>02:31 recv_sid==02:31>00:05 >> endianness==LE recv_buff_size==10880 send_buff_size==10880 >> [TRACE] [RFNOC] [RFNoC Factory] block_ctrl_base::make() >> [DEBUG] [RFNOC] Reading XML file /usr/share/uhd/rfnoc/blocks/duc.xml >> for NOC ID 0xD0C0000000000002 >> [TRACE] [RFNOC] [RFNoC Factory] Using controller key 'DUC' and block >> name 'DUC' >> [DEBUG] [RFNOC] Reading XML file /usr/share/uhd/rfnoc/blocks/duc.xml >> for NOC ID 0xD0C0000000000002 >> [INFO] [0/DUC_0] Initializing block control (NOC ID: >> 0xD0C0000000000002) >> [DEBUG] [0/DUC_0] Checking compat number for FPGA component >> `noc_shell': Expecting 5.1, actual: 5.1. >> [TRACE] [0/DUC_0] Adding port definition at xbar/DUC_0/ports/in/0: type >> = 'sc16' pkt_size = '0' vlen = '0' >> [TRACE] [0/DUC_0] Adding port definition at xbar/DUC_0/ports/in/1: type >> = 'sc16' pkt_size = '0' vlen = '0' >> [TRACE] [0/DUC_0] Adding port definition at xbar/DUC_0/ports/out/0: >> type = 'sc16' pkt_size = '0' vlen = '0' >> [TRACE] [0/DUC_0] Adding port definition at xbar/DUC_0/ports/out/1: >> type = 'sc16' pkt_size = '0' vlen = '0' >> [TRACE] [RFNOC] [NocScript] Executing and asserting code: >> GE($input_rate, 0.0) >> [TRACE] [RFNOC] [NocScript] Executing and asserting code: >> GE($output_rate, 0.0) >> [TRACE] [RFNOC] [NocScript] Executing and asserting code: >> GE($fullscale, 0.0) >> [TRACE] [RFNOC] [NocScript] Executing and asserting code: >> GE($input_rate, 0.0) >> [TRACE] [RFNOC] [NocScript] Executing and asserting code: >> GE($output_rate, 0.0) >> [TRACE] [RFNOC] [NocScript] Executing and asserting code: >> GE($fullscale, 0.0) >> [DEBUG] [0/DUC_0] Loading DUC with 1 halfbands and max CIC >> interpolation 8 >> [DEBUG] [DUC] Checking compat number for FPGA component `DUC': >> Expecting 2.0, actual: 2.0. >> [TRACE] [RFNOC] [NocScript] Executing and asserting code: >> GE($input_rate, 0.0) >> [TRACE] [RFNOC] [NocScript] Executing and asserting code: >> GE($input_rate, 0.0) >> [DEBUG] [MPMD] Adding RPC access to block: 0/Radio_0 Block args: >> mgmt_addr=127.0.0.1,type=e3xx,product=e310_sg1,serial=309C7C2,claimed=F >> alse,fpga=filethatdoesntexist >> [INFO] [0/Radio_0] RX freq = 2.4e+09 >> [INFO] [0/Radio_0] RX band = 6 >> [INFO] [0/Radio_0] RX SW1 = 5 >> [INFO] [0/Radio_0] RX SWC = 0 >> [INFO] [0/Radio_0] RX SWB = 1 >> [INFO] [0/Radio_0] RX VCRX_SW = 1 >> [INFO] [0/Radio_0] RX VCTXRX_SW = 0 >> [INFO] [0/Radio_0] RX freq = 2.4e+09 >> [INFO] [0/Radio_0] RX band = 6 >> [INFO] [0/Radio_0] RX SW1 = 5 >> [INFO] [0/Radio_0] RX SWC = 0 >> [INFO] [0/Radio_0] RX SWB = 1 >> [INFO] [0/Radio_0] RX VCRX_SW = 1 >> [INFO] [0/Radio_0] RX VCTXRX_SW = 0 >> [INFO] [0/Radio_0] RX freq = 2.4e+09 >> [INFO] [0/Radio_0] RX band = 6 >> [INFO] [0/Radio_0] RX SW1 = 5 >> [INFO] [0/Radio_0] RX SWC = 0 >> [INFO] [0/Radio_0] RX SWB = 1 >> [INFO] [0/Radio_0] RX VCRX_SW = 1 >> [INFO] [0/Radio_0] RX VCTXRX_SW = 0 >> [INFO] [0/Radio_0] RX freq = 2.4e+09 >> [INFO] [0/Radio_0] RX band = 6 >> [INFO] [0/Radio_0] RX SW1 = 5 >> [INFO] [0/Radio_0] RX SWC = 0 >> [INFO] [0/Radio_0] RX SWB = 1 >> [INFO] [0/Radio_0] RX VCRX_SW = 1 >> [INFO] [0/Radio_0] RX VCTXRX_SW = 0 >> [INFO] [0/Radio_0] RX freq = 2.4e+09 >> [INFO] [0/Radio_0] RX band = 6 >> [INFO] [0/Radio_0] RX SW1 = 5 >> [INFO] [0/Radio_0] RX SWC = 0 >> [INFO] [0/Radio_0] RX SWB = 1 >> [INFO] [0/Radio_0] RX VCRX_SW = 1 >> [INFO] [0/Radio_0] RX VCTXRX_SW = 0 >> [INFO] [0/Radio_0] RX freq = 2.4e+09 >> [INFO] [0/Radio_0] RX band = 6 >> [INFO] [0/Radio_0] RX SW1 = 5 >> [INFO] [0/Radio_0] RX SWC = 0 >> [INFO] [0/Radio_0] RX SWB = 1 >> [INFO] [0/Radio_0] RX VCRX_SW = 1 >> [INFO] [0/Radio_0] RX VCTXRX_SW = 0 >> [DEBUG] [0/Radio_0] Master Clock Rate is: 16 MHz. >> [DEBUG] [0/Radio_0] Asking for clock rate 16 MHz >> >> [DEBUG] [0/Radio_0] Actual clock rate 16 MHz >> >> [DEBUG] [CORES] Performing timer loopback test... >> [DEBUG] [CORES] Timer loopback test passed. >> [DEBUG] [0/Radio_0] Asking for clock rate 30.72 MHz >> >> [DEBUG] [0/Radio_0] Actual clock rate 30.72 MHz >> >> [DEBUG] [CORES] Performing timer loopback test... >> [DEBUG] [CORES] Timer loopback test passed. >> [INFO] [0/Radio_0] Performing CODEC loopback test... >> [INFO] [0/Radio_0] CODEC loopback test passed >> [DEBUG] [0/Radio_0] Asking for clock rate 16 MHz >> >> [DEBUG] [0/Radio_0] Actual clock rate 16 MHz >> >> [DEBUG] [CORES] Performing timer loopback test... >> [DEBUG] [CORES] Timer loopback test passed. >> [DEBUG] [0/Radio_0] Asking for clock rate 30.72 MHz >> >> [DEBUG] [0/Radio_0] Actual clock rate 30.72 MHz >> >> [DEBUG] [CORES] Performing timer loopback test... >> [DEBUG] [CORES] Timer loopback test passed. >> [INFO] [0/Radio_0] Performing CODEC loopback test... >> [INFO] [0/Radio_0] CODEC loopback test passed >> [DEBUG] [0/Radio_0] Asking for clock rate 16 MHz >> >> [DEBUG] [0/Radio_0] Actual clock rate 16 MHz >> >> [DEBUG] [CORES] Performing timer loopback test... >> [DEBUG] [CORES] Timer loopback test passed. >> _____________________________________________________ >> / >> | Device: E300-Series Device >> | _____________________________________________________ >> | / >> | | Mboard: ni-e31x-309C7C2F >> | | mpm_version: 3.15.0.git-g6563c537 >> | | pid: 30674 >> | | product: e310_sg1 >> | | rev: 4 >> | | rpc_connection: local >> | | serial: 309C7C2 >> | | type: e3xx >> | | MPM Version: 1.2 >> | | FPGA Version: 1.0 >> | | FPGA git hash: f52a643.clean >> | | RFNoC capable: Yes >> | | >> | | Time sources: internal, external, gpsdo >> | | Clock sources: internal >> | | Sensors: ref_locked, temp_fpga, temp_mb >> | | _____________________________________________________ >> | | / >> | | | RX Dboard: A >> | | | _____________________________________________________ >> | | | / >> | | | | RX Frontend: 0 >> | | | | Name: E3xx >> | | | | Antennas: RX2, TX/RX >> | | | | Sensors: lo_locked, rssi, lo_lock, ad9361_temperature >> | | | | Freq range: 70.000 to 6000.000 MHz >> | | | | Gain range PGA: 0.0 to 76.0 step 1.0 dB >> | | | | Bandwidth range: 20000000.0 to 40000000.0 step 0.0 Hz >> | | | | Connection Type: IQ >> | | | | Uses LO offset: No >> | | | _____________________________________________________ >> | | | / >> | | | | RX Frontend: 1 >> | | | | Name: E3xx >> | | | | Antennas: RX2, TX/RX >> | | | | Sensors: lo_locked, rssi, lo_lock, ad9361_temperature >> | | | | Freq range: 70.000 to 6000.000 MHz >> | | | | Gain range PGA: 0.0 to 76.0 step 1.0 dB >> | | | | Bandwidth range: 20000000.0 to 40000000.0 step 0.0 Hz >> | | | | Connection Type: IQ >> | | | | Uses LO offset: No >> | | | _____________________________________________________ >> | | | / >> | | | | RX Codec: A >> | | | | Name: AD9361 Dual ADC >> | | | | Gain Elements: None >> | | _____________________________________________________ >> | | / >> | | | TX Dboard: A >> | | | _____________________________________________________ >> | | | / >> | | | | TX Frontend: 0 >> | | | | Name: E3xx >> | | | | Antennas: TX/RX >> | | | | Sensors: lo_locked, ad9361_temperature >> | | | | Freq range: 47.000 to 6000.000 MHz >> | | | | Gain range PGA: 0.0 to 89.8 step 0.2 dB >> | | | | Bandwidth range: 20000000.0 to 40000000.0 step 0.0 Hz >> | | | | Connection Type: IQ >> | | | | Uses LO offset: No >> | | | _____________________________________________________ >> | | | / >> | | | | TX Frontend: 1 >> | | | | Name: E3xx >> | | | | Antennas: TX/RX >> | | | | Sensors: lo_locked, ad9361_temperature >> | | | | Freq range: 47.000 to 6000.000 MHz >> | | | | Gain range PGA: 0.0 to 89.8 step 0.2 dB >> | | | | Bandwidth range: 20000000.0 to 40000000.0 step 0.0 Hz >> | | | | Connection Type: IQ >> | | | | Uses LO offset: No >> | | | _____________________________________________________ >> | | | / >> | | | | TX Codec: A >> | | | | Name: AD9361 Dual DAC >> | | | | Gain Elements: None >> | | _____________________________________________________ >> | | / >> | | | RFNoC blocks on this device: >> | | | >> | | | * Radio_0 >> | | | * DDC_0 >> | | | * DUC_0 >> >> >> >> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
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