Hi Andrew,

This is an issue we are aware of related to the RFNoC DDC/DUC blocks. We
are working on a fix and expect to have in a future release of UHD.

Regards,
Nate Temple

On Mon, Jan 28, 2019 at 10:11 AM Andrew Danowitz via USRP-users <
usrp-users@lists.ettus.com> wrote:

> I have an RFNOC block that, based on a control register can either
> decimate the signal it's working on or leave the output rate the same as
> the input rate. If I set the control register to an initial value (either
> decimate, or not decimate) and let the system run, it works fine in either
> mode. If I try to change the decimation mode while the block is running, I
> start getting timeout errors. I currently use the axi_rate_change block to
> help handle the rate change, and have tried to synchronize changing the
> block's mode (decimate or not) with the axi_rate_change's clear_user flag.
> Any thoughts?
>
> Thanks,
> Andrew
>
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